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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 4 • Date April 2006

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

A low-power ROM using single charge-sharing capacitor and hierarchical bit line

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems

Energy-efficient soft error-tolerant digital signal processing

Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

VLSI implementation of low-power high-quality color interpolation processor for CCD camera

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers

Design and implementation of a high-speed matrix multiplier based on word-width decomposition

Coding schemes for chip-to-chip interconnect applications

Linear-programming-based techniques for synthesis of network-on-chip architectures

Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing

A low power turbo/Viterbi decoder for 3GPP2 applications

Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs

Special section on autonomous silicon validation and testing of microprocessors and microprocessor-based systems

Special section on system on chip integration

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