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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 7 • Date July 2006

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Displaying Results 1 - 24 of 24
  • Table of contents

    Publication Year: 2006, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2006, Page(s): c2
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  • A digital design flow for secure integrated circuits

    Publication Year: 2006, Page(s):1197 - 1208
    Cited by:  Papers (39)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB) | HTML iconHTML

    Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation, and other information leaked by the switching behavior of digital complementary metal-oxide-semiconductor (CMOS) gates. This paper presents a digital very large sca... View full abstract»

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  • Exact and approximate algorithms for the extension of embedded processor instruction sets

    Publication Year: 2006, Page(s):1209 - 1229
    Cited by:  Papers (86)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1187 KB) | HTML iconHTML

    In embedded computing, cost, power, and performance constraints call for the design of specialized processors, rather than for the use of the existing off-the-shelf solutions. While the design of these application-specific CPUs could be tackled from scratch, a cheaper and more effective option is that of extending the existing processors and toolchains. Extensibility is indeed a feature now offere... View full abstract»

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  • Complexity of two-level logic minimization

    Publication Year: 2006, Page(s):1230 - 1246
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (335 KB) | HTML iconHTML

    The complexity of two-level logic minimization is a topic of interest to both computer-aided design (CAD) specialists and computer science theoreticians. In the logic synthesis community, two-level logic minimization forms the foundation for more complex optimization procedures that have significant real-world impact. At the same time, the computational complexity of two-level logic minimization h... View full abstract»

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  • Efficient modeling of 1/f/sup /spl alpha// noise using multirate process

    Publication Year: 2006, Page(s):1247 - 1256
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (833 KB) | HTML iconHTML

    In order to verify the system performance of mixed-signal systems on chip (SoCs), computer-aided design (CAD) tools are required to generate 1/falpha noise that degrades the performance of most analog circuits. Current techniques for generating discrete sequences of 1/falpha noise require a large amount of computations that place an excessive burden on the computation engine ... View full abstract»

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  • On symbolic model order reduction

    Publication Year: 2006, Page(s):1257 - 1272
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (527 KB) | HTML iconHTML

    Symbolic model order reduction (SMOR) is a macromodeling technique that generates reduced-order models while retaining the parameters in the original models. Such symbolic reduced-order models can be repeatedly simulated with a greater efficiency for varying model parameters. Although the model-order-reduction concept has been extensively developed in literature and widely applied in a variety of ... View full abstract»

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  • Statistical interconnect metrics for physical-design optimization

    Publication Year: 2006, Page(s):1273 - 1288
    Cited by:  Papers (19)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB) | HTML iconHTML

    In this paper, statistical models for the efficient analysis of interconnect delay and crosstalk noise in the presence of back-end process variations are developed. The proposed models enable closed-form computation of means and variances of interconnect-delay, crosstalk-noise peak, and coupling-induced-delay change for given magnitudes of variation in relevant process parameters, such as linewidt... View full abstract»

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  • Profile-guided microarchitectural floor planning for deep submicron processor design

    Publication Year: 2006, Page(s):1289 - 1300
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (547 KB) | HTML iconHTML

    As very large scale integration (VLSI) process technology migrates to nanoscale with a feature size of less than 100 nm, global wire delay is becoming a major hindrance in keeping the latency of intrachip communication within a single cycle, thus substantially decaying performance scalability. In addition, an effective microarchitectural floor planning algorithm can no longer ignore the dynamic co... View full abstract»

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  • Wirelength minimization for min-cut placements via placement feedback

    Publication Year: 2006, Page(s):1301 - 1312
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (555 KB) | HTML iconHTML

    The advent of strong multilevel partitioners has made top-down min-cut placers a favored choice for modern placer implementations. Terminal propagation is an important step in min-cut placers because it translates partitioning results into global-placement wirelength assumptions. In this work, the repartitioning problem is carefully reexamined (Proc. ACM/IEEE Int. Symp. Physical Design, p. 18, 199... View full abstract»

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  • Min-cut floorplacement

    Publication Year: 2006, Page(s):1313 - 1326
    Cited by:  Papers (43)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1074 KB) | HTML iconHTML

    Large macro blocks, predesigned datapaths, embedded memories, and analog blocks are increasingly used in application-specific integrated circuit (ASIC) designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature. Large macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical pl... View full abstract»

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  • A statistical methodology for wire-length prediction

    Publication Year: 2006, Page(s):1327 - 1336
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (487 KB) | HTML iconHTML

    In this paper, the classic wire-length estimation problem is addressed and a new statistical wire-length estimation approach that captures the probability distribution function of net lengths after placement and before routing is proposed. These types of models are highly instrumental in formalizing a complete and consistent probabilistic approach to design automation and design closure where, alo... View full abstract»

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  • Battery-aware power management based on Markovian decision processes

    Publication Year: 2006, Page(s):1337 - 1349
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (539 KB) | HTML iconHTML

    This paper addresses the problem of maximizing the capacity utilization of the battery power source in a portable electronic system under latency and loss rate constraints. First, a detailed stochastic model of a power-managed battery-powered electronic system is presented. The model, which is based on the theories of continuous-time Markovian decision processes (CTMDP) and stochastic networks, ca... View full abstract»

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  • Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing

    Publication Year: 2006, Page(s):1350 - 1367
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (922 KB) | HTML iconHTML

    As semiconductor technology advances into the nanoscale era and more functional blocks are added into systems-on-chip, the interface between circuit design and manufacturing is becoming blurred. An increasing number of features, traditionally ignored by designers, are influencing both circuit performance and yield. As a result, design tools need to incorporate new factors. One important source of ... View full abstract»

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  • An integrated DFT solution for mixed-signal SOCs

    Publication Year: 2006, Page(s):1368 - 1377
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (270 KB) | HTML iconHTML

    This paper introduces an efficient implementation of a test access mechanism (TAM) for mixed-signal system-on-chip (MSOC) testing. The design-for-testability (DFT) strategy has been developed to make the testing of analog cores digitally compliant. The mixed-signal cores have been accessed through specially design mechanisms (switches). A computer-aided test (CAT) tool employing the proposed algor... View full abstract»

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  • Orthonormal bandlimited Kautz sequences for global system modeling from piecewise rational models

    Publication Year: 2006, Page(s):1377 - 1381
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (226 KB) | HTML iconHTML

    Frequency-domain rational macromodeling techniques have to be limited to relatively small frequency ranges or to a limited number of poles, mostly due to numerical issues. A pertinent problem in system modeling is therefore to come up with a global broad-band macromodel, given a number of piecewise rational, possibly disjoint, small-band models. We describe an effective implementation procedure, b... View full abstract»

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  • Arithmetic transforms for compositions of sequential and imprecise datapaths

    Publication Year: 2006, Page(s):1382 - 1391
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (401 KB) | HTML iconHTML

    This paper addresses the issue of obtaining compact canonical representations of datapath circuits with sequential elements for the purpose of equivalence checking and component matching. First, the authors demonstrate the mechanisms for an efficient compositional construction of the arithmetic transform (AT), which is the underlying function representation used in modern word-level decision diagr... View full abstract»

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  • Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation

    Publication Year: 2006, Page(s):1392 - 1400
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    Efficient dc fault simulation of nonlinear analog circuits is addressed in this paper. Two techniques, one-step relaxation and adaptive simulation continuation, are proposed. By one-step relaxation, only one Newton-Raphson iteration is performed for each faulty circuit with the dc solution of the good circuit as the initial point, and the approximate solution is used for detecting the fault. The p... View full abstract»

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  • Analytical model for crosstalk and intersymbol interference in point-to-point buses

    Publication Year: 2006, Page(s):1400 - 1410
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (357 KB) | HTML iconHTML

    In this paper, an analytical model to estimate crosstalk noise and intersymbol interference on capacitively and inductively coupled point-to-point on-chip buses is derived. The derived closed-form equation for output voltage enables the usage of the model in computer-aided design (CAD) tools for complex systems where high simulation speed is essential. The model also combines together properties s... View full abstract»

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  • Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip

    Publication Year: 2006, Page(s):1411 - 1418
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (342 KB) | HTML iconHTML

    The continued push to smaller geometries, higher frequencies, and larger chip sizes rapidly resulted in an incompatibility between interconnect needs and projected interconnect performance. As stated in the 2003 International Technology Roadmap for Semiconductors (ITRS'03) report, revolutionary interconnect methodologies such as radio frequency (RF)/wireless will deliver the foreseen progress in s... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2006, Page(s): 1419
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  • IEEE Biomedical Circuits and Systems Conference healthcare technology (BiOCAS 2006)

    Publication Year: 2006, Page(s): 1420
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2006, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2006, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu