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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 7 • Date July 2006

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  • Table of contents

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

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  • A digital design flow for secure integrated circuits

    Page(s): 1197 - 1208
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    Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation, and other information leaked by the switching behavior of digital complementary metal-oxide-semiconductor (CMOS) gates. This paper presents a digital very large scale integrated (VLSI) design flow to create secure power-analysis-attack-resistant ICs. The design flow starts from a normal design in a hardware description language such as very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) or Verilog and provides a direct path to an SCA-resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. The basis for power analysis attack resistance is discussed. This paper describes how to adjust the library databases such that the regular single-ended static CMOS standard cells implement a dynamic and differential logic style and such that 20 000+ differential nets can be routed in parallel. This paper also explains how to modify the constraints and rules files for the synthesis, place, and differential route procedures. Measurement-based experimental results have demonstrated that the secure digital design flow is a functional technique to thwart side-channel power analysis. It successfully protects a prototype Advanced Encryption Standard (AES) IC fabricated in an 0.18-mum CMOS View full abstract»

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  • Exact and approximate algorithms for the extension of embedded processor instruction sets

    Page(s): 1209 - 1229
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    In embedded computing, cost, power, and performance constraints call for the design of specialized processors, rather than for the use of the existing off-the-shelf solutions. While the design of these application-specific CPUs could be tackled from scratch, a cheaper and more effective option is that of extending the existing processors and toolchains. Extensibility is indeed a feature now offered in real designs, e.g., by processors such as Tensilica Xtensa [T. R. Halfhill, Microprocess Rep., 2003], ARC ARCtangent [T. R. Halfhill, Microprocess Rep., 2000], STMicroelectronics ST200 [P. Faraboschi, G. Brown, J. A. Fisher, G. Desoli, and F. Homewood, Proc. 27th Annu. Int. Symp. Computer Architecture, 2000, p. 203], and MIPS CorExtend [T. R. Halfhill, Microprocess Rep., 2003]. While all these processors provide development environments with simulation capabilities for evaluating efficiently hand-crafted solutions, the tools to identify automatically the best processor configuration for a given application are less common. In particular, solutions to choose specialized instruction-set extensions (ISEs) have been investigated in the past years but are still seldom part of commercial toolchains. This paper provides a formal methodology and a set of algorithms that help address the problem. It proposes exact algorithms to derive optimal ISEs; exact identification of a single ISE is applicable to basic blocks of up to 1500 assembler-like instructions. This paper also introduces approximate methods that can process basic blocks of larger size. Results show that the described algorithms find solutions close to those that a designer would obtain by a detailed study of the application code. Both heuristic and exact algorithms find ISEs able to speed up unextended processors up to 5.0x. State-of-the-art comparisons show that the presented algorithms outperform existing ones by up to 2.6x View full abstract»

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  • Complexity of two-level logic minimization

    Page(s): 1230 - 1246
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    The complexity of two-level logic minimization is a topic of interest to both computer-aided design (CAD) specialists and computer science theoreticians. In the logic synthesis community, two-level logic minimization forms the foundation for more complex optimization procedures that have significant real-world impact. At the same time, the computational complexity of two-level logic minimization has posed challenges since the beginning of the field in the 1960s; indeed, some central questions have been resolved only within the last few years, and others remain open. This recent activity has classified some logic optimization problems of high practical relevance, such as finding the minimal sum-of-products (SOP) form and maximal term expansion and reduction. This paper surveys progress in the field with self-contained expositions of fundamental early results, an account of the recent advances, and some new classifications. It includes an introduction to the relevant concepts and terminology from computational complexity, as well a discussion of the major remaining open problems in the complexity of logic minimization View full abstract»

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  • Efficient modeling of 1/f/sup /spl alpha// noise using multirate process

    Page(s): 1247 - 1256
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    In order to verify the system performance of mixed-signal systems on chip (SoCs), computer-aided design (CAD) tools are required to generate 1/falpha noise that degrades the performance of most analog circuits. Current techniques for generating discrete sequences of 1/falpha noise require a large amount of computations that place an excessive burden on the computation engine and random number generators. In this paper, the authors propose a low-complexity 1/falpha noise generation scheme, which is based on a multirate filter bank. In this scheme, each branch in the filter bank processes signals in a different frequency band while allowing for arbitrary selection of alpha in each bank. The proposed approach greatly reduces computations when compared to traditional noise generation processes of using a single noise-shaping filter. Furthermore, it allows selecting different combinations of noise frequency response in different frequency bands, thus allowing calibration of noise generated in simulation to the one measured in the laboratory from test chips. A comparison of various noise generation schemes is also presented View full abstract»

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  • On symbolic model order reduction

    Page(s): 1257 - 1272
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    Symbolic model order reduction (SMOR) is a macromodeling technique that generates reduced-order models while retaining the parameters in the original models. Such symbolic reduced-order models can be repeatedly simulated with a greater efficiency for varying model parameters. Although the model-order-reduction concept has been extensively developed in literature and widely applied in a variety of problems, model order reduction from a symbolic perspective has not been well studied. Several methods developed in this paper include symbol isolation, nominal projection, and first-order approximation. These methods can be applied to models having only a few parametric elements and to models having many symbolic elements. Of special practical interest are models that have slightly varying parameters such as process related variations, for which efficient reduction procedures can be developed. Each technique proposed in this paper has been tested by circuit examples. Experiments show that the proposed methods are efficient and effective for many circuit problems View full abstract»

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  • Statistical interconnect metrics for physical-design optimization

    Page(s): 1273 - 1288
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    In this paper, statistical models for the efficient analysis of interconnect delay and crosstalk noise in the presence of back-end process variations are developed. The proposed models enable closed-form computation of means and variances of interconnect-delay, crosstalk-noise peak, and coupling-induced-delay change for given magnitudes of variation in relevant process parameters, such as linewidth, metal thickness, metal spacing, and interlayer dielectric (ILD) thickness. The proposed approach is based on the observation that if the variations in different physical dimensions are assumed to be independent normal random variables, then the interconnect behavior also tends to have a Gaussian distribution. In the proposed statistical models, delay and noise are expressed directly as functions of changes in physical parameters. This formulation allows us to preserve all correlations and can be very useful in evaluating delay and noise sensitivities due to changes in various physical dimensions. For interconnect-delay computation, the authors express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. They show that ignoring higher order terms in the resulting variational moments does not result in a loss of accuracy. Finally, these variability-aware moments are used in known closed-form delay and slew metrics to compute interconnect-delay probability density functions (pdfs). Similarly for coupling noise and dynamic-delay analysis, the authors rely on the linearity (Gaussian) assumption, allowing us to truncate nonlinear terms and express noise and dynamic-delay pdfs as linear functions of variations in relevant geometric dimensions. They compare their approach to SPICE-based Monte Carlo simulations and report the error in mean and standard deviation of interconnect delay to be 1% and 4% on average, respectively View full abstract»

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  • Profile-guided microarchitectural floor planning for deep submicron processor design

    Page(s): 1289 - 1300
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    As very large scale integration (VLSI) process technology migrates to nanoscale with a feature size of less than 100 nm, global wire delay is becoming a major hindrance in keeping the latency of intrachip communication within a single cycle, thus substantially decaying performance scalability. In addition, an effective microarchitectural floor planning algorithm can no longer ignore the dynamic communication patterns of applications. This article, using the profile information acquired at the microarchitecture level, proposes a "profile-guided microarchitectural floor planner" that considers both the impact of wire delay and the architectural behavior, namely, the intermodule communication, to reduce the latency of frequent routes inside a processor and to maintain performance scalability. Based on the simulation results here, the proposed profile-guided method shows a 5%-40% average instructions per cycle (IPC) improvement when the clock frequency is fixed. From the perspective of instruction throughput in billion instructions per second (BIPS), the floor planner is much more scalable than the conventional wirelength-based floor planner View full abstract»

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  • Wirelength minimization for min-cut placements via placement feedback

    Page(s): 1301 - 1312
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    The advent of strong multilevel partitioners has made top-down min-cut placers a favored choice for modern placer implementations. Terminal propagation is an important step in min-cut placers because it translates partitioning results into global-placement wirelength assumptions. In this work, the repartitioning problem is carefully reexamined (Proc. ACM/IEEE Int. Symp. Physical Design, p. 18, 1997) in the context of terminal propagation and studied in an in-depth manner. Abstractly, it was observed that in repartitioning, future cell locations are used for present terminal propagations and that this can be conceptually regarded as a form of placement feedback. This concept was utilized to achieve accurate terminal propagation via feedback iteration and controller insertion to fine-tune the feedback response. This yields substantial reductions in placement wirelength. Implementing our approach in Capo [version 8.7 (Proc. ACM/IEEE Design Automation Conf., p. 477, 2000 and GSRC Bookshelf)] and applying it to standard benchmark circuits yields up to 14% wirelength reductions for the IBM benchmarks with an average improvement of 5.5% and up to 10% reductions for the Peko benchmarks with an average improvement of 5.37%. Experiments also show consistent improvements for routed wirelength, yielding up to 9% wirelength reductions and 5.8% average reduction with acceptable increase in placement runtime. In practice, the method proposed significantly improves routability without building congestion maps and also reduces the number of vias View full abstract»

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  • Min-cut floorplacement

    Page(s): 1313 - 1326
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    Large macro blocks, predesigned datapaths, embedded memories, and analog blocks are increasingly used in application-specific integrated circuit (ASIC) designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature. Large macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical placement. On the other hand, traditional floorplanning techniques do not scale to large numbers of objects, especially in terms of solution quality. The authors propose to integrate min-cut placement with fixed-outline floorplanning to solve the more general placement problem, which includes cell placement, floorplanning, mixed-size placement, and achieving routability. At every step of min-cut placement, either partitioning or wirelength-driven fixed-outline floorplanning is invoked. If the latter fails, the authors undo an earlier partitioning decision, merge adjacent placement regions, and refloorplan the larger region to find a legal placement for the macros. Empirically, this framework improves the scalability and quality of results for traditional wirelength-driven floorplanning. It has been validated on recent designs with embedded memories and accounts for routability. Additionally, the authors propose that free-shape rectilinear floorplanning can be used with rough module-area estimates before logic synthesis View full abstract»

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  • A statistical methodology for wire-length prediction

    Page(s): 1327 - 1336
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    In this paper, the classic wire-length estimation problem is addressed and a new statistical wire-length estimation approach that captures the probability distribution function of net lengths after placement and before routing is proposed. These types of models are highly instrumental in formalizing a complete and consistent probabilistic approach to design automation and design closure where, along with optimizing the pertinent cost function, the associated prediction error is also considered. The wire-length prediction model was developed using a combination of parametric and nonparametric statistical techniques. The model predicts not only the length of the net using input parameters extracted from the floorplan of a design, but also probability distributions that a net with given characteristics after placement will have a particular length. The model is validated using the learn-and-test and resubstitution techniques. The model can be used for a variety of purposes, including the generation of a large number of statistically sound, and therefore realistic, instances of designs. The net models were applied to the probabilistic buffer-insertion problem and substantial improvement was obtained in net delay after routing (~ 20%) when compared to a traditional bounding box (BBOX)-based buffer-insertion strategy View full abstract»

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  • Battery-aware power management based on Markovian decision processes

    Page(s): 1337 - 1349
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    This paper addresses the problem of maximizing the capacity utilization of the battery power source in a portable electronic system under latency and loss rate constraints. First, a detailed stochastic model of a power-managed battery-powered electronic system is presented. The model, which is based on the theories of continuous-time Markovian decision processes (CTMDP) and stochastic networks, captures two important characteristics of today's rechargeable battery cells; i.e., the current rate-capacity characteristic and the relaxation induced capacity recovery. Next, the battery-aware dynamic power management (DPM) problem is formulated as a policy optimization problem and is solved by using a linear programming approach. Experimental results show that the proposed method outperforms existing methods by more than 20% in terms of battery service lifetime View full abstract»

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  • Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing

    Page(s): 1350 - 1367
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    As semiconductor technology advances into the nanoscale era and more functional blocks are added into systems-on-chip, the interface between circuit design and manufacturing is becoming blurred. An increasing number of features, traditionally ignored by designers, are influencing both circuit performance and yield. As a result, design tools need to incorporate new factors. One important source of circuit-performance degradation comes from deterministic within-die variation from lithography imperfections and Cu-interconnect chemical-mechanical polishing (CMP). To determine how these within-die variations impact circuit performance, we need a new analysis tool. Thus, we have proposed a methodology to involve layout-dependent within-die variations in static timing analysis. Our methodology combines a set of scripts and commercial tools to analyze a full chip. The tool has been applied to analyze delay of ISCAS85 benchmark circuits in the presence of imperfect lithography and CMP variation View full abstract»

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  • An integrated DFT solution for mixed-signal SOCs

    Page(s): 1368 - 1377
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    This paper introduces an efficient implementation of a test access mechanism (TAM) for mixed-signal system-on-chip (MSOC) testing. The design-for-testability (DFT) strategy has been developed to make the testing of analog cores digitally compliant. The mixed-signal cores have been accessed through specially design mechanisms (switches). A computer-aided test (CAT) tool employing the proposed algorithm has been developed. Extensive experiments have been performed on MSOC benchmarks built of ISCAS'89 circuits for digital cores and ITC'97 circuits for analog cores. Results show that the CAT tool provides a hardware-efficient integrated solution View full abstract»

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  • Orthonormal bandlimited Kautz sequences for global system modeling from piecewise rational models

    Page(s): 1377 - 1381
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    Frequency-domain rational macromodeling techniques have to be limited to relatively small frequency ranges or to a limited number of poles, mostly due to numerical issues. A pertinent problem in system modeling is therefore to come up with a global broad-band macromodel, given a number of piecewise rational, possibly disjoint, small-band models. We describe an effective implementation procedure, based on orthonormal bandlimited Kautz sequences. As a first step, we show how a truncated Kautz basis can be obtained directly from a judiciously chosen state-space description. Next, having incorporated the bandlimitedness requirement, we obtain imbeddable orthonormal bandlimited Kautz sequences. A numerical procedure for calculating the underlying bandlimited scalar products and Grammians, as applied to piecewise bandlimited state-space data, is implemented and tested View full abstract»

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  • Arithmetic transforms for compositions of sequential and imprecise datapaths

    Page(s): 1382 - 1391
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    This paper addresses the issue of obtaining compact canonical representations of datapath circuits with sequential elements for the purpose of equivalence checking and component matching. First, the authors demonstrate the mechanisms for an efficient compositional construction of the arithmetic transform (AT), which is the underlying function representation used in modern word-level decision diagrams (WLDDs). Second, presented is a way of generating the canonical transforms of the sequential and imprecise datapath circuits View full abstract»

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  • Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation

    Page(s): 1392 - 1400
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    Efficient dc fault simulation of nonlinear analog circuits is addressed in this paper. Two techniques, one-step relaxation and adaptive simulation continuation, are proposed. By one-step relaxation, only one Newton-Raphson iteration is performed for each faulty circuit with the dc solution of the good circuit as the initial point, and the approximate solution is used for detecting the fault. The paper shows experimentally and justifies theoretically that approximate dc fault simulation by one-step relaxation can accomplish almost the same fault coverage as exact dc fault simulation. Exact dc fault simulation by adaptive simulation continuation is first to order faulty circuits based on the results of one-step relaxation, and then to use the solution of the previous faulty circuit as the initial point for the Newton-Raphson iteration of the next faulty circuit. Experiments on a set of 29 MCNC Circuit Simulation and Modeling Workshop benchmark circuits show that exact dc fault simulation by adaptive simulation continuation can achieve an average speedup of 4.4 and as high as 15 over traditional stand-alone fault simulation View full abstract»

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  • Analytical model for crosstalk and intersymbol interference in point-to-point buses

    Page(s): 1400 - 1410
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    In this paper, an analytical model to estimate crosstalk noise and intersymbol interference on capacitively and inductively coupled point-to-point on-chip buses is derived. The derived closed-form equation for output voltage enables the usage of the model in computer-aided design (CAD) tools for complex systems where high simulation speed is essential. The model also combines together properties such as inductive coupling, initial conditions, signal rise time, input phases, and bit sequences that have not been included in a single closed-form model before. The model is compared to HSPICE and previous models. The model and HSPICE are in good agreement with each other View full abstract»

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  • Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip

    Page(s): 1411 - 1418
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    The continued push to smaller geometries, higher frequencies, and larger chip sizes rapidly resulted in an incompatibility between interconnect needs and projected interconnect performance. As stated in the 2003 International Technology Roadmap for Semiconductors (ITRS'03) report, revolutionary interconnect methodologies such as radio frequency (RF)/wireless will deliver the foreseen progress in semiconductor technology. Recent advances in silicon integrated circuit technique are making possible tiny low-cost transceivers to be integrated on chip, namely "radio-on-chip" (ROC) technology. This paper proposes the idea of using wireless radios to transmit test data and control signals to resolve the acerbated core accessibility problem. Three types of wireless test micronetworks are first presented, i.e., miniature wireless local area network (LAN), multihop wireless test control network (MTCNet), and distributed multihop MTCNet. Then, the test control overhead and system resource partitioning in on-chip wireless micronetworks are analyzed. Several challenging system design problems such as RF node placement, core clustering, and control routing are studied, and the test control resources (i.e., the on-chip RF nodes for intrachip communication) are properly distributed and system optimization is performed in terms of test control cost. A simulation study shows the feasibility and applicability of intrachip MTCNet View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Page(s): 1419
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  • IEEE Biomedical Circuits and Systems Conference healthcare technology (BiOCAS 2006)

    Page(s): 1420
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu