Scheduled System Maintenance
On Wednesday, December 20, IEEE Xplore will undergo scheduled maintenance from 1:00-5:00 PM ET.
During this time, there may be intermittent impact on performance. We apologize for any inconvenience.

IEEE Design & Test of Computers

Issue 3 • May-June 2006

Filter Results

Displaying Results 1 - 25 of 26
  • [Front cover]

    Publication Year: 2006, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (672 KB)
    Freely Available from IEEE
  • [Inside front cover]

    Publication Year: 2006, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (214 KB)
    Freely Available from IEEE
  • IEEE Computer Society Celebrates Two 60-Year Anniversaries

    Publication Year: 2006, Page(s): 177
    Request permission for commercial reuse | PDF file iconPDF (624 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2006, Page(s):178 - 179
    Request permission for commercial reuse | PDF file iconPDF (290 KB)
    Freely Available from IEEE
  • Masthead

    Publication Year: 2006, Page(s): 180
    Request permission for commercial reuse | PDF file iconPDF (39 KB)
    Freely Available from IEEE
  • The Need for a SiP Design and Test Infrastructure

    Publication Year: 2006, Page(s): 181
    Cited by:  Papers (1)
    Request permission for commercial reuse | PDF file iconPDF (136 KB) | HTML iconHTML
    Freely Available from IEEE
  • DAC Highlights

    Publication Year: 2006, Page(s):182 - 184
    Request permission for commercial reuse | PDF file iconPDF (86 KB)
    Freely Available from IEEE
  • 2006 Latin American Test Workshop

    Publication Year: 2006, Page(s): 185
    Request permission for commercial reuse | PDF file iconPDF (51 KB) | HTML iconHTML
    Freely Available from IEEE
  • Guest Editors' Introduction: Big Innovations in Small Packages

    Publication Year: 2006, Page(s):186 - 187
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (51 KB) | HTML iconHTML

    Conventional single-die microelectronic packages on a printed circuit board have been with us for a long time. These electronic packages provide a means of interconnecting, powering, cooling, and protecting integrated circuit chips. Today, system-in-package (SiP) provides a variety of packaging requirements for computer, consumer, aerospace, military, and medical electronic applications by stackin... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cell phone integration: SiP, SoC, and PoP

    Publication Year: 2006, Page(s):188 - 195
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    Engineers must make many cost-effective decisions during a product's design cycle. One challenge is deciding on the best packaging for their products. This article presents trade-offs among system-in-package, system-on-chip, and package-on-package integration for mobile phone applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Chip-package codesign flow for mixed-signal SiP designs

    Publication Year: 2006, Page(s):196 - 202
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB) | HTML iconHTML

    Design engineers are challenged with two separate entities: the chip and package designs. Because system-in-package integrates multiple dies into a package, design engineers should have a tool to easily combine the two entities. This article demonstrates a seven-die SiP design that implements a chip-and-package codesign platform using available EDA tools View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System-in-package testing: problems and solutions

    Publication Year: 2006, Page(s):203 - 211
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (471 KB) | HTML iconHTML

    System-in-package integrates multiple dies in a common package. Therefore, testing SiP technology is different from system-on-chip, which integrates multiple vendor parts. This article provides test strategies for known good die and known good substrate in the SiP. Case studies prove feasibility using the IEEE 1500 test structure View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Packaging a 40-Gbps serial link using a wire-bonded plastic ball grid array

    Publication Year: 2006, Page(s):212 - 219
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB) | HTML iconHTML

    System-in-package provides highly integrated packaging with high-speed performance. Many SiP packages contain low-cost 3D stacked chips interconnected by fine wire bonds. In a high-frequency spectrum, these wire bonds can cause discontinuities causing signal degradation. This article addresses problems with wire bonding in high-frequency SiP packages and proposes design methodologies to reduce the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Electronic system, platform, and package codesign

    Publication Year: 2006, Page(s):220 - 233
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (189 KB) | HTML iconHTML

    Integrating multicore heterogeneous systems into a system-in-package has challenged many design and test engineers. To overcome these obstacles, we need a common EDA tool for digital, analog, RF, and thermal designs. This article proposes a platform-centric design methodology for modern electronic systems that could incorporate system-on-chip, system-in-package, and system-on-package technologies View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs

    Publication Year: 2006, Page(s):234 - 243
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (402 KB) | HTML iconHTML

    Testing mixed-signal circuits remains one of the most difficult challenges within the semiconductor industry. In this article, the authors present a novel DFT technique to test sets of ADCs and DACs embedded in a complex SiP. The technique provides fully digital testing on the converters to significantly reduce the cost of testing View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE Computer Society Membership Information

    Publication Year: 2006, Page(s): 244
    Request permission for commercial reuse | PDF file iconPDF (496 KB)
    Freely Available from IEEE
  • 2006 IEEE Computer Society Professional Membership/Subscription Application

    Publication Year: 2006, Page(s):245 - 246
    Request permission for commercial reuse | PDF file iconPDF (1952 KB)
    Freely Available from IEEE
  • IEEE Computer Society Information

    Publication Year: 2006, Page(s): 247
    Request permission for commercial reuse | PDF file iconPDF (59 KB)
    Freely Available from IEEE
  • The First Transaction, but not the Last

    Publication Year: 2006, Page(s):248 - 249
    Request permission for commercial reuse | PDF file iconPDF (80 KB) | HTML iconHTML
    Freely Available from IEEE
  • Test Technology Technical Council Newsletter

    Publication Year: 2006, Page(s): 250
    Request permission for commercial reuse | PDF file iconPDF (23 KB)
    Freely Available from IEEE
  • Advertiser/Product Index

    Publication Year: 2006, Page(s): 251
    Request permission for commercial reuse | PDF file iconPDF (147 KB)
    Freely Available from IEEE
  • CEDA Currents

    Publication Year: 2006, Page(s):252 - 253
    Request permission for commercial reuse | PDF file iconPDF (106 KB)
    Freely Available from IEEE
  • Call for Papers: Special Issue on Advances in Functional Validation through Hybrid Techniques

    Publication Year: 2006, Page(s): 254
    Request permission for commercial reuse | PDF file iconPDF (37 KB)
    Freely Available from IEEE
  • IEEE Computer Society Digital Library Packages for Institutions

    Publication Year: 2006, Page(s): 255
    Request permission for commercial reuse | PDF file iconPDF (99 KB)
    Freely Available from IEEE
  • Is System in Package the Panacea for Integration?

    Publication Year: 2006, Page(s): 256
    Cited by:  Papers (2)
    Request permission for commercial reuse | PDF file iconPDF (44 KB) | HTML iconHTML
    Freely Available from IEEE

Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty