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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 5 • Date May 2006

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Displaying Results 1 - 25 of 29
  • Table of contents

    Page(s): c1 - c4
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): c2
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  • Low-hardware complexity PRBGs based on a piecewise-linear chaotic map

    Page(s): 329 - 333
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    In this brief, a family of discretized one-dimensional chaotic maps derived from the Sawtooth map is analyzed to evaluate its suitability for the integrated implementation of low-complexity digital pseudorandom bit generators (PRBGs). The proposed PRBGs, classifiable as nonlinear congruential generators, are investigated in terms of period length, statistical properties of the generated sequences, hardware complexity, and are compared with traditional PRBGs. View full abstract»

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  • Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors

    Page(s): 334 - 338
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    One of the most attractive features of MOBILE-based circuits is their self-latching operation, which allows pipelining at the gate level, and thus very high through-output, without any area overhead associated to the addition of the latches. However, the self-latching behavior is not inherent to the practical circuit topologies employed to implement MOBILE circuits. This paper reports on very simple MOBILE structures supporting this statement. The analysis performed is useful in extracting design guidelines to guarantee the required behavior. View full abstract»

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  • Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits

    Page(s): 339 - 343
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    In this brief, we address the combined application of word-length allocation and architectural synthesis of linear time-invariant digital signal processing systems. These two design tasks are traditionally performed sequentially, thus lessening the overall design complexity, but ignoring forward and backward dependencies that may lead to cost reductions. Mixed integer linear programming is used to formulate the combined problem and results are compared to the two-step traditional approach. View full abstract»

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  • A novel noise-shaping DAC for multi-bit sigma-delta modulator

    Page(s): 344 - 348
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    This paper describes a new noise-shaping technique for reducing the noise of the internal digital-analog conversion (DAC) in multi-bit low-pass sigma-delta modulators. The proposed technique works with most existing dynamic element matching (DEM) algorithms to provide noise shaping to the DAC noise. The simulation shows that a 10-dB improvement in the signal-to-noise conversion ratio can be obtained with the proposed noise-shaping with DEM (NSDEM) technique. A dithered DAC employing NSDEM is realized in a 0.35-μm CMOS process and the test result shows the first-order high-pass noise shaping to the DAC noise, and validates the proposed concept. View full abstract»

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  • Bias compensation based recursive least-squares identification algorithm for MISO systems

    Page(s): 349 - 353
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    For multi-input single-output output-error systems, the least-squares (LS) estimates are biased. In order to obtain the unbiased estimates, we present a recursive LS identification algorithm based on a bias compensation technique. The basic idea is to eliminate the estimation bias by adding a correction term in the LS estimates, and further to derive a bias compensation based recursive LS algorithm. Finally, we test the proposed algorithms by simulation and show their effectiveness. View full abstract»

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  • An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays

    Page(s): 354 - 358
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB) |  | HTML iconHTML  

    Massively parallel processor-per-pixel single-instruction multiple data arrays are being successfully used for early vision applications in smart sensor systems; however, they are inherently inefficient when executing algorithms involving propagation of binary signals, such as the geodesic reconstruction. Yet, these algorithms, at the interface between pixel-level and object-level image processing, should be implemented on the vision chip to facilitate data reduction at the sensor level. A cellular asynchronous network is presented in this paper, which can be used to execute binary propagation operations. The proposed circuit is optimized in terms of speed and power consumption. In 0.35-μm technology, the simulated propagation speed is 0.18 ns per pixel and the total energy expended per propagation is 0.37 pJ per cell. In this brief, implementation issues are discussed and simulation results including image processing examples are presented. View full abstract»

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  • Watermark detection for noisy interpolated images

    Page(s): 359 - 363
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    In this brief, the case where the watermark is detected in a noisy interpolated version of the originally watermarked image is investigated. Polyphase decomposition is utilized at the detection side in order to enable the flexible formation of a fused image, which is appropriate for watermark detection. The optimal fused correlator, obtained by combining information from different image components, is derived through a statistical analysis of the correlation detector properties, followed by Lagrange optimization. It is shown that it is preferable to perform detection in a fused image rather than the original image. View full abstract»

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  • A technique to increase the efficiency of high-voltage charge pumps

    Page(s): 364 - 368
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    A charge pump that utilizes a MOSFET body diode as a charge transfer switch is discussed. The body diode is characterized and a body diode model is developed for simulating the charge pump circuit. A 10% increase of voltage gain has been achieved in the proposed switching technique when compared with a traditional Dickson charge pump. The top plate and bottom plate switching technique have also been illustrated to improve the efficiency of the charge pump. A six-stage Dickson charge pump was designed to produce a 19 V output from a 3.3-V supply, using a 4 MHz, two-phase nonoverlapping clock signal driving the charge pump. The design was fabricated in a 0.35-μm SOI CMOS process. An efficiency of 79% is achieved at a load current of approximately 19 μA. View full abstract»

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  • RC-RCD clamp circuit for ringing losses reduction in a flyback converter

    Page(s): 369 - 373
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    An RCD clamp circuit is usually used in flyback converters, in order to limit the voltage spikes caused by leakage transformer inductance. Oscillation ringing appears due to the clamp diode, which deteriorates the converter's power rate. This brief describes this ringing phenomenon and the use of an RC-RCD clamp circuit for damping the clamp diode's oscillation. This clamp circuit is capable for improving a flyback converter's power ratio. View full abstract»

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  • Carry-free approximate squaring functions with O(n) complexity and O(1) delay

    Page(s): 374 - 378
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    This paper presents two simple combinational logic design approaches for bit-parallel approximate squarers of unsigned numbers. The design approaches are suitable for squarers of any bit length, and are particularly well suited for implementation in look-up table-based field-programmable gate arrays. It is shown that the hardware requirements grow linearly with the input bit width, as opposed to recent work where the complexity grows quadratically. This is a consequence of the optimized function selection algorithm which limits the number of input variables to each bit function. It is also shown that the critical path delay is independent of the input bit width. The proposed sets of Boolean equations are very simple to use and lend themselves very well to a parameterized HDL description. For a 7-bit input, the maximum relative error (MRE) and average relative error (ARE) are as low as 9.44% and 2.47%, respectively. For very wide input, the best MRE and ARE figures asymptotically approach 11.3% and 4.5%. View full abstract»

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  • A weighted least squares approach to the design of FIR filters synthesized using the modified frequency response masking structure

    Page(s): 379 - 383
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    This paper presents an application of the weighted least squares (WLS) method to the design of sharp linear phase finite-impulse response (FIR) digital filters synthesized using a modified frequency-response masking (FRM) structure. In our approach, the original minimax design problem is converted into a WLS problem. The WLS problem is highly nonlinear with respect to the coefficients of the filter. However, it can be decomposed into four linear least squares (LS) problems, each of which can be solved analytically. The design problem is then solved iteratively by using an alternating variable approach. The effectiveness of the method is demonstrated through solving a low-pass linear phase sharp FIR digital filter example. View full abstract»

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  • A connectivity based clustering algorithm with application to VLSI circuit partitioning

    Page(s): 384 - 388
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    Circuit partitioning is a fundamental problem in very large-scale integration (VLSI) physical design automation. In this brief, we present a new connectivity-based clustering algorithm for VLSI circuit partitioning. The proposed clustering method focuses on capturing natural clusters in a circuit, i.e., the groups of cells that are highly interconnected in a circuit. Therefore, the proposed clustering method can reduce the size of large-scale partitioning problems without losing partitioning solution qualities. The performance of the proposed clustering algorithm is evaluated on a standard set of partitioning benchmarks-ISPD98 benchmark suite. The experimental results show that by applying the proposed clustering algorithm, the previously reported best partitioning solutions from state-of-the-art partitioners are further improved. View full abstract»

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  • A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC

    Page(s): 389 - 393
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    This paper describes a fast digital background calibration algorithm for pipeline or cyclic analog-to-digital converters. The proposed method corrects for the finite gain/bandwidth of the interstage operational amplifier and for capacitor mismatch in multiplying digital-to-analog converters stages. The new algorithm, fast gain error correction, converges more than 100 times faster than other correlation-based correction techniques presented in literature. The high speed of convergence of the error estimation is due to the use of a polynomial interpolation that cancel the interference in the error estimation process caused by the input signal. This new method does not need any added analog circuitry, does not perturb the output samples, and requires only a digital finite-impulse response filter to implement the polynomial interpolation as opposed to existing fast converging correlation techniques. View full abstract»

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  • A dual voltage-frequency VLSI chip for image watermarking in DCT domain

    Page(s): 394 - 398
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB) |  | HTML iconHTML  

    In this brief, we present a new VLSI architecture that can insert invisible or visible watermarks in images in the discrete cosine transform domain. The proposed architecture incorporates low-power techniques such as dual voltage, dual frequency, and clock gating to reduce the power consumption and exploits pipelining and parallelism extensively in order to achieve high performance. The supply voltage level and the operating frequency are chosen for each module so as to maintain the required bandwidth and throughput match among the different modules. A prototype VLSI chip was designed and verified using various Cadence and Synopsys tools based on TSMC 0.25-μm technology with 1.4 M transistors and 0.3 mW of estimated dynamic power. View full abstract»

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  • Sigma-delta modulators operating at a limit cycle

    Page(s): 399 - 403
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB) |  | HTML iconHTML  

    A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital-analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs. View full abstract»

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  • The universal opamp and applications in continuous-time resistorless and capacitorless linear weighted voltage addition

    Page(s): 404 - 408
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    A versatile analog building block denoted the universal operational amplifier (opamp) is introduced. The circuit is a generalized version of the fully differential difference opamp with 2n weighted differential inputs. Applications in resistorless and capacitorless continuous-time linear weighted voltage addition are discussed. Experimental results of a test chip prototype are shown that validate the proposed approach. Simulations show potential for high frequency operation of the circuit with gain-bandwidth close to 140 MHz in 0.5-μm CMOS technology. View full abstract»

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  • Simple instability criterion for a class of uncertain discrete systems

    Page(s): 409 - 411
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    In this note, the instability of a class of uncertain discrete systems is investigated. Simple instability criterion is derived to guarantee the instability of such systems. Finally, a numerical example is provided to illustrate the main result. View full abstract»

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  • A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-μm CMOS technology

    Page(s): 412 - 416
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62°, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-μm CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass ΣΔ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a ±1.25-V supply. View full abstract»

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  • A differential pulsewidth control loop for high-speed VLSI systems

    Page(s): 417 - 421
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    For those adopting double data rate technology systems, the precise system timing plays a crucial role since both rising and falling edges of the system clock signal are used to sample the input data. Due to this requirement, it is necessary to accurately maintain the duty cycle of the clock signal at 50%. For a multistage clock buffer, a pulsewidth control loop (PWCL) circuit was therefore proposed to adjust the duty cycle of its output signal. This paper is aimed at introducing a new proposed differential PWCL (DPWCL) together with investigating its mechanism through a comprehensive theoretical analysis. By taking advantage of a differential topology, the dc offset in generating the control voltage can be removed thereby improving the duty cycle control accuracy. Moreover, the proposed DPWCL employs a low-pass filter to generate the reference voltage so that the DPWCL does not necessitate a 50% duty cycle reference clock. View full abstract»

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  • The 10th IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA 2006)

    Page(s): 422
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  • IEEE Biomedical Circuits and Systems Conference healthcare technology (BiOCAS 2006)

    Page(s): 423
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    Freely Available from IEEE
  • Special issue on nanoelectronic circuits and nanoarchitectures

    Page(s): 424
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    Freely Available from IEEE
  • 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2006)

    Page(s): 425
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    Freely Available from IEEE

Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope