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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 5 • Date May 2006

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Displaying Results 1 - 25 of 29
  • Table of contents

    Publication Year: 2006 , Page(s): c1 - c4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2006 , Page(s): c2
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  • Distortion analysis of Miller-compensated three-stage amplifiers

    Publication Year: 2006 , Page(s): 961 - 976
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (960 KB) |  | HTML iconHTML  

    This paper proposes a theoretical approach for evaluating distortion in the frequency domain of three-stage amplifiers adopting two commonly used compensation techniques, namely the nested Miller (NM) and the reversed NM. The analysis is based on appropriate amplifier modeling and on the assumption that the nonlinearity generated by each stage is static. Calculations are thus greatly simplified avoiding complex methods based on the Volterra series. Only dominant contributions need to be taken into account, thereby highlighting those mechanisms generating distortion and their features in the frequency domain. Moreover, the adopted approach provides useful design guidelines and explains why the NM compensation technique allows generally better linearity performance at low frequency and why the reversed NM is best suited to high frequencies. Simulation results with Spectre on two transistor-level CMOS circuits are also provided and found to be in very good agreement with expected results. View full abstract»

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  • Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology

    Publication Year: 2006 , Page(s): 977 - 983
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-μm digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 μArms. The input sensitivity of the receiver front-end is 16 μA for 2.5-Gbps operation with bit-error rate less than 10-12, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 μm×1500 μm. View full abstract»

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  • Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation

    Publication Year: 2006 , Page(s): 984 - 991
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB) |  | HTML iconHTML  

    Circuit techniques using resistor strings (R-strings) and resistor rings (R-rings) for phase averaging and interpolation are described. Phase averaging can reduce phase errors, and phase interpolation can increase the number of available phases. In addition to the waveform shape, the averaging and the interpolation performances of the R-strings and R-rings are determined by the clock frequency normalized by a RC time constant of the circuits. To attain better phase accuracy, a smaller RC time constant is required, but at the expense of larger power dissipation. To demonstrate the resistor ring's capability of phase averaging and interpolation, a 125-MHz 8-bit digital-to-phase converter (DPC) was designed and fabricated using a standard 0.35-μm SPQM CMOS technology. Measurement results show that the DPC attains 8-bit resolution using the proposed phase averaging and interpolation technique. View full abstract»

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  • Chameleon: a dual-mode 802.11b/Bluetooth receiver system design

    Publication Year: 2006 , Page(s): 992 - 1003
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1056 KB)  

    In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the expected receiver nonidealities and the characteristics of each building block are evaluated through bit-error-rate simulations. The proposed receiver design is verified through a fully integrated implementation from low-noise amplifier to analog-to-digital converter using IBM 0.25-μm BiCMOS technology. Experimental results from the integrated prototype meet the specifications from both standards and are in good agreement with the target sensitivity. View full abstract»

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  • On incremental sigma-delta modulation with optimal filtering

    Publication Year: 2006 , Page(s): 1004 - 1015
    Cited by:  Papers (15)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1232 KB)  

    The paper presents a quantization-theoretic framework for studying incremental sigma-delta (ΣΔ) data conversion systems. The framework makes it possible to efficiently compute the quantization intervals and hence the transfer function of the quantizer, and to determine the mean square error (MSE) and maximum error for the optimal and conventional linear filters for first and second order incremental ΣΔ modulators. The results show that the optimal filter can significantly outperform conventional linear filters in terms of both MSE and maximum error. The performance of conventional ΣΔ data converters is then compared to that of incremental ΣΔ with optimal filtering for bandlimited signals. It is shown that incremental ΣΔ can outperform the conventional approach in terms of signal-to-noise-and-distortion ratio. The framework is also used to provide a simpler and more intuitive derivation of the Zoomer algorithm. View full abstract»

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  • High-order electromechanical ΣΔ modulation in micromachined inertial sensors

    Publication Year: 2006 , Page(s): 1016 - 1022
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    Analysis of second-order electromechanical sigma-delta (ΣΔ) inertial sensors shows that in-band quantization error introduces a resolution penalty, which cannot be eliminated by oversampling. In addition, a tradeoff between resolution and phase compensation forces such systems to operate with reduced phase margin. This paper introduces high-order electromechanical ΣΔ modulation as an approach, which eliminates the quantization noise overhead and allows for increased phase compensation without degrading the resolution. Quasi-linear analysis is used to evaluate the contribution of the individual noise sources to the output of the system and to examine the effect of noise interaction on the behavior of electromechanical ΣΔ modulators. View full abstract»

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  • CMOS RF receiver system design: a systematic approach

    Publication Year: 2006 , Page(s): 1023 - 1034
    Cited by:  Papers (20)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB) |  | HTML iconHTML  

    A unified system-level design methodology for highly integrated CMOS radio frequency receiver design is introduced. This complete system-level design methodology is targeted to minimize the total power consumption of the receiver. System-level design techniques which can be used to derive the overall receiver radio specifications and study noise and linearity performance of receivers are presented. Then, a few circuit examples of building blocks in receiver signal chain are analyzed to show a linear relationship between power and dynamic range of the blocks. The result is then used to derive the optimal system specification distribution among receiver signal chain building blocks yielding the minimum total receiver power consumption for a given system performance. The theory and an actual CMOS Bluetooth receiver design are compared showing very good agreement. View full abstract»

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  • Digit-pipelined direct digital frequency synthesis based on differential CORDIC

    Publication Year: 2006 , Page(s): 1035 - 1044
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB) |  | HTML iconHTML  

    A novel direct digital frequency synthesis (DDFS) architecture based on the differential CORDIC (DCORDIC) algorithm is presented. The architecture allows digit-level pipelining in the CORDIC angle path by implementing a two-dimensional systolic array. Unlike other DDFS architectures, it incorporates the phase accumulator in the digit-level pipelining framework so that a bottleneck-free datapath throughout the whole system is achieved in a scalable manner. A generic environment that generates fully synthesizable Verilog codes that implement the proposed architecture is created and the physical attributes of the resulting system are discussed. View full abstract»

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  • Loosely coupled memory-based decoding architecture for low density parity check codes

    Publication Year: 2006 , Page(s): 1045 - 1056
    Cited by:  Papers (27)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB) |  | HTML iconHTML  

    Parallel decoding is required for low density parity check (LDPC) codes to achieve high decoding throughput, but it suffers from a large set of registers and complex interconnections due to randomly located 1's in the sparse parity check matrix. This paper proposes a new LDPC decoding architecture to reduce registers and alleviate complex interconnections. To reduce the number of messages to be exchanged among processing units (PUs), two data flows that can be loosely coupled are developed by allowing duplicated operations. In addition, intermediate values are grouped and stored into local storages each of which is accessed by only one PU. In order to save area, local storages are implemented using memories instead of registers. A partially parallel architecture is proposed to promote the memory usage and an efficient algorithm that schedules the processing order of the partially parallel architecture is also proposed to reduce the overall processing time by overlapping operations. To verify the proposed architecture, a 1024 bit rate-1/2 LDPC decoder is implemented using a 0.18-μm CMOS process. The decoder runs correctly at the frequency of 200 MHz, which enables almost 1 Gbps decoding throughput. Since the proposed decoder occupies an area of 10.08 mm2, it is less than one fifth of area compared to the previous architecture. View full abstract»

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  • Thresholding noise-free ordered mean filter based on Dempster-Shafer theory for image restoration

    Publication Year: 2006 , Page(s): 1057 - 1064
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1216 KB) |  | HTML iconHTML  

    This work proposes a new decision-based filter, the thresholding noise-free ordered mean (TNOM) filter based on the Dempster-Shafer (D-S) evidence theory, to preserve more details of images than can other decision-based filters, while effectively suppressing impulse noise. The new filter mechanism is composed of an efficient D-S impulse detector and a noise filter that works by estimating the central noise-free ordered mean (CNOM) value. The D-S evidence theory provides a way to deal with the uncertainty in the evidence and information fusion. Pieces of evidence are extracted, and the mass functions defined using the local information in the filter window. Then, the decision rule is applied to determine whether noise exists, according to the final combined belief value. If a pixel is detected to be a corrupted pixel, then the proposed filter will be triggered to replace it. Otherwise, the pixel is kept unchanged. With respect to the noise suppression of noise on both fixed-valued and random-valued impulses without smearing the fine details in the image, extensive simulation results reveal that the proposed scheme significantly outperforms other decision-based filters. View full abstract»

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  • Scalable and modular memory-based systolic architectures for discrete Hartley transform

    Publication Year: 2006 , Page(s): 1065 - 1077
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB) |  | HTML iconHTML  

    In this paper, we present a design framework for scalable memory-based implementation of the discrete Hartley transform (DHT) using simple and efficient systolic and systolic-like structures for short and prime transform lengths, as well as, for lengths 4 and 8. We have used the proposed short-length structures to construct highly modular architectures for higher transform lengths by a new prime-factor implementation approach. The structures proposed for the prime-factor DHT, interestingly, do not involve any transposition hardware/time. Besides, it is shown here that an N-point DHT can be computed efficiently from two (N/2)-point DHTs of its even- and odd-indexed input subsequences in a recursive manner using a ROM-based multiplication stage. Apart from flexibility of implementation, the proposed structures offer significantly lower area-time complexity compared with the existing structures. The proposed schemes of computation of the DHT can conveniently be scaled not only for higher transform lengths but also according to the hardware constraint or the throughput requirement of the application. View full abstract»

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  • A mesochronous pipelining scheme for high-performance digital systems

    Publication Year: 2006 , Page(s): 1078 - 1088
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1136 KB) |  | HTML iconHTML  

    A novel mesochronous pipelining scheme is described in this paper. In this scheme, data and clock travel together. At any given time a pipeline stage could be operating on more than one data wave. The clock period in the proposed pipeline scheme is determined by the pipeline stage with largest difference between its minimum and maximum delays. This is a significant performance gain compared to conventional pipeline scheme where clock period is determined by the stage with the largest delay. A detailed analysis of the clock period constraints is provided to show the performance gains and Speedup of mesochronous pipelining over other pipelining schemes. Also, the number of pipeline stages and pipeline registers is small. The clock distribution scheme is simple in the mesochronous pipeline architecture. An 8 × 8-bit carry-save adder multiplier has been implemented in mesochronous pipeline architecture using modest TSMC 180-nm (drawn length 200 nm) CMOS technology. The multiplier architecture and simulation results are described in detail in this paper. The pipelined multiplier is able to operate on a clock period of 350 ps (2.86 GHz). This is a Speedup of 1.7 times over conventional pipeline scheme, with fewer pipeline stages and pipeline registers. View full abstract»

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  • Optimal bus sizing in migration of processor design

    Publication Year: 2006 , Page(s): 1089 - 1100
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB) |  | HTML iconHTML  

    The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor to next generation technology. In this paper, timing optimization of signal buses is performed by resizing and spacing individual bus wires, while the area of the whole bus structure is regarded as a fixed constraint. Four different objective functions are defined and their usefulness is discussed in the context of the layout migration process. The paper presents solutions for the respective optimization problems and analyzes their properties. In an optimally-tuned bus layout, after optimizing the most critical signal delay, all signal delays (or slacks) are equal. The optimal solution of the MinMax problem is always bounded by the solution of the corresponding sum-of-delays problem. An iterative algorithm to find the optimally-tuned bus layout is presented. Examples of solutions are shown, and design implications are derived and discussed. View full abstract»

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  • An extension of the channel-assignment problem: L(2, 1)-labelings of generalized Petersen graphs

    Publication Year: 2006 , Page(s): 1101 - 1107
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    The channel-assignment problem involves assigning frequencies represented by nonnegative integers to radio transmitters such that transmitters in close proximity receive frequencies that are sufficiently far apart to avoid interference. In one of its variations, the problem is commonly quantified as follows: transmitters separated by the smallest unit distance must be assigned frequencies that are at least two apart and transmitters separated by twice the smallest unit distance must be assigned frequencies that are at least one apart. Naturally, this channel-assignment problem can be modeled with vertex labelings of graphs. An L(2, 1)-labeling of a graph G is a function f from the vertex set V(G) to the nonnegative integers such that |f(x)-f(y)|≥2 if d(x,y)=1 and |f(x)-f(y)|≥1 if d(x,y)=2. The λ-number of G, denoted λ(G), is the smallest number k such that G has an L(2, 1)-labeling using integers from {0,1,...,k}. A long-standing conjecture by Griggs and Yeh stating that λ(G) can not exceed the square of the maximum degree of vertices in G has motivated the study of the λ-numbers of particular classes of graphs. This paper provides upper bounds for the λ-numbers of generalized Petersen graphs of orders 6, 7, and 8. The results for orders 7 and 8 establish two cases in a conjecture by Georges and Mauro, while the result for order 6 improves the best known upper bound. Furthermore, this paper provides exact values for the λ-numbers of all generalized Petersen graphs of order 6. View full abstract»

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  • Digital Laguerre filter design with maximum passband-to-stopband energy ratio subject to peak and Group delay constraints

    Publication Year: 2006 , Page(s): 1108 - 1118
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB) |  | HTML iconHTML  

    In this paper, we formulate a general design of transversal filter structures with maximum relative passband-to-stopband energy ratio subject to complex frequency response constraints in the passband and the stopband as well as additional constraints such as constraints. These constraints are important for applications where the suppression of noise at certain frequencies are important. Additional constraints are introduced allowing approximately linear phase and constant group delay in the passband. For a given set of basis functions, the design problem can be formulated as a semi-infinite quadratic optimization problem in the filter coefficients, which are the decision variables to be optimized. In this paper, we focus on the design of digital Laguerre filter and digital finite impulse response (FIR) filter structures. A modified bridging algorithm is developed for searching for the optimum pole of the Laguerre filters. Design examples are given to demonstrate the effectiveness of the proposed algorithm. View full abstract»

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  • Matrix decomposition and butterfly diagrams for mutual relations between Hadamard-Haar and arithmetic spectra

    Publication Year: 2006 , Page(s): 1119 - 1129
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB) |  | HTML iconHTML  

    The mutual relationships between Hadamard-Haar and Arithmetic transforms and their corresponding spectra in the form of matrix decomposition as layered vertical and horizontal Kronecker matrices are discussed here together with their proofs, fast algorithms, and computational costs. The new relations apply to an arbitrary dimension of the transform matrices and allow performing direct conversions between Arithmetic and Hadamard-Haar functions and their corresponding spectra. In addition, analysis of butterfly diagrams for these new relations is also introduced and it is shown that they are more efficient than the matrix decomposition method. View full abstract»

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  • Two-variable polynomials: intersecting zeros and stability

    Publication Year: 2006 , Page(s): 1130 - 1139
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    In order to construct two-variable polynomials with a certain zero behavior, the notion of intersecting zeros is studied. We show that generically two-variable polynomials have a finite set of intersecting zeros, and give an algorithm on how to construct a polynomial with the desired intersecting zeros. Relations with the Cayley-Bacharach theorem are addressed. In addition, we will also address the case when stable polynomials are sought. View full abstract»

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  • Designing security for number sequences generated by means of the sawtooth chaotic map

    Publication Year: 2006 , Page(s): 1140 - 1150
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    In the paper, we describe how to design the security of number sequences generated by a generator, exploiting the concept of partition of the state space of the sawtooth chaotic map into disjoint subspaces. We prove that the generator can generate nonperiodic and periodic sequences with arbitrary order of elements when the map is implemented in an uncountable set, and periodic sequences with arbitrary order of elements when the map is implemented in a countable set. The numerical security of the generated sequences is shown to be comparable when we limit our observations to finite time intervals. A method of designing the security of sequences produced by the generator was proposed. It was also demonstrated that the existence of methods for reconstructing the linear congruential generator does not imply automatic reconstruction of the generator, exploiting the concept of partition of the state space of the sawtooth map implemented in a finite-state machine. View full abstract»

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  • Wide-band system identification using multiple tones with allpass filters and square-law detectors

    Publication Year: 2006 , Page(s): 1151 - 1165
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB) |  | HTML iconHTML  

    This paper introduces a method of wide-band system identification that uses a uniformly spaced set of tones with allpass filters and square-law detectors to obtain estimates of amplitude and phase at the associated discrete frequencies. The bandwidth of the detectors is on the order of the tone spacing and so can be much smaller than the overall signal bandwidth, thereby making feasible the use of low-cost analog RF integrated circuits and/or pure digital signal processing with all of its inherent advantages. Applications of this technique include equalization and compensation for fiber optic and wide-band cellular communication systems. View full abstract»

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  • On Schur stable multivariate polynomials

    Publication Year: 2006 , Page(s): 1166 - 1173
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    The class of stable multivariate polynomials, recently introduced by Kaczorek (1985), is the largest class of polynomials preserving the stability property under small coefficient variations. The principal goal of the contribution is to show that the class of Schur stable multivariate polynomials is the Moebius transformation of the latter one. This fundamental relation provides a vehicle to translate results known for one class to the other one. View full abstract»

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  • Constrained shortest link-disjoint paths selection: a network programming based approach

    Publication Year: 2006 , Page(s): 1174 - 1187
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB) |  | HTML iconHTML  

    Given a graph G with each link in the graph associated with two positive weights, cost and delay, we consider the problem of selecting a set of k link-disjoint paths from a node s to another node t such that the total cost of these paths is minimum and that the total delay of these paths is not greater than a specified bound. This problem, to be called the constrained shortest link-disjoint path (CSDP(k)) problem, can be formulated as an integer linear programming (ILP) problem. Relaxing the integrality constraints results in an upper bounded linear programming problem. We first show that the integer relaxations of the CSDP(k) problem and a generalized version of this problem to be called the generalized CSDP (GCSDP (k)) problem (in which each path is required to satisfy a specified bound on its delay) both have the same optimal objective value. In view of this, we focus our work on the relaxed form of the CSDP(k) problem (RELAX-CSDP(k)). We study RELAX-CSDP(k) from the primal perspective using the revised simplex method of linear programming. We discuss different issues such as formulas to identify entering and leaving variables, anti-cycling strategy, computational time complexity etc., related to an efficient implementation of our approach. We show how to extract from an optimal solution to RELAX-CSDP(k) a set of k link-disjoint s-t paths which is an approximate solution to the original CSDP(k) problem. We also derive bounds on the quality of this solution with respect to the optimum. We present simulation results that demonstrate that our algorithm is faster than currently available approaches. Our simulation results also indicate that in most cases the individual delays of the paths produced starting from RELAX-CSDP(k) do not deviate in a significant way from the individual path delay requirements of the GCSDP(k) problem. View full abstract»

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  • Special issue on nanoelectronic circuits and nanoarchitectures

    Publication Year: 2006 , Page(s): 1188
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    Freely Available from IEEE
  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2006 , Page(s): 1189
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    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras