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Advanced Packaging, IEEE Transactions on

Issue 2 • Date May 2006

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Displaying Results 1 - 25 of 32
  • Table of contents

    Page(s): c1 - 201
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  • IEEE Transactions on Advanced Packaging publication information

    Page(s): c2
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  • Very high density interconnect elastomer chip sockets

    Page(s): 202 - 210
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2304 KB) |  | HTML iconHTML  

    The integration of more and more functionality into smaller and smaller form factor electronic products, drives the need for denser chip to substrate interconnect systems. As the number of I/O pins increases, the use of area array chips or packages becomes inevitable. Metal patterned elastomer chip sockets have now been improved to work with contact densities as high as 80 000 contacts/cm2 corresponding to a pitch of 36 μm. Sockets with 10 000 contacts and a 72-μm pitch have survived more than 400 cycles in air-to-air thermal cycling chambers as well as freezing shocks caused by dipping into liquid nitrogen. Although the daisy chain test circuits breaks for temperatures lower than -50°C and higher than 90°C, they always return to the initial resistance values when entering the normal temperature range. The combination of a gold-to-gold contact interface and the elastic features of the contact bumps makes this socket an ideal compliance layer between bare chips and different types of carrier substrates, reducing the problems caused by thermomechanical mismatch between the substrate and the chip. Bad dies can easily be replaced, since the chip is not soldered or glued to the socket. The size and the possibility to control the geometry of the contacts provides means to maintain a good high-frequency characteristic impedance matching all the way to the chip pad. View full abstract»

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  • Novel method for simultaneous formation of wires and vias of a printed circuit board using nanoporous body

    Page(s): 211 - 217
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    A new type of a flexible printed circuit board with landless vias is developed using a novel method called interconnection via nanoporous structure (INPS). This method can make wires and vias of the printed circuit board simultaneously by a single photo-exposure process. A new photo-induced selective plating method was used to impregnate a nanoporous substrate with copper, and a new photomask was designed, which constitutes of a completely vacant large hole for via and aggregation patterns of very fine holes for wire. Because of the simple process, the INPS board is characterized by landless vias and very fine circuit. Owing to the structure, it is also characterized by flexibility and detachable wires. View full abstract»

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  • Bumpless interconnect through ultrafine Cu electrodes by means of surface-activated bonding (SAB) method

    Page(s): 218 - 226
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    In this paper, we demonstrate the feasibility of ultrahigh-density bumpless interconnect by realizing the ultrafine pitch bonding of Cu electrodes at room temperature. The bumpless interconnect is a novel concept of bonding technology that enables a narrow bonding pitch of less than 10 μm by overcoming the thermal strain problem. In the bumpless structure, two thin layers including an insulator and metallic interconnections on the same surface are bonded at room temperature by the surface-activated bonding (SAB) method. In order to realize the bumpless interconnect, we invented a SAB flip-chip bonder that enabled the alignment accuracy of ±1 μm in the high vacuum condition. Moreover, the fabrication process of ultrafine Cu electrodes was developed by using the damascene process and reactive ion beam etching (RIE) process, and the bumpless electrodes of 3 μm in diameter, 10 μm in pitch, and 60 nm in height were formed. As a result, we succeeded in the interconnection of 100 000 bumpless electrodes with the interfacial resistance of less than 1 mΩ. An increase of the resistance was considerably small after thermal aging at 150°C for 1000 h. View full abstract»

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  • The development of Cu bonding wire with oxidation-resistant metal coating

    Page(s): 227 - 231
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    Although Cu bonding wire excels over Au bonding wire in some respects such as production costs, it has not been widely used because of its poor bondability at second bonds due to surface oxidation. We conceived an idea of electroplating oxidation-resistant metal on the Cu bonding wire to prevent the surface oxidation. The electroplating of Au, Ag, Pd, and Ni over Cu bonding wire all increased bond strengths as expected, but it caused problematic ball shapes except Pd-plated Cu bonding wire. The wire could produce the same ball shape as that of Au bonding wire. It was also proved to have excellent bondability sufficient to replace Au bonding wire. That is, it excelled in bond strengths, defective bonding ratio, and wideness of "Parameter Windows". It also showed the same stability as Au bonding wire in reliability tests, while bonds of Cu bonding wire were deteriorated in a few of the tests. In short, the Pd-plated Cu bonding wire can realize excellent bonding similar to Au bonding wire, while having much lower production costs. View full abstract»

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  • Novel process warpage modeling of matrix stacked-die BGA

    Page(s): 232 - 239
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    A comprehensive warpage analysis is performed on the matrix stacked-die ball grid array BGA (SDBGA) by means of finite-element modeling and experimental warpage measurements. By comparing the block warpage results from conventional linear small deformation simulation and the experimental measurement results, it is found that the linear method is not able to capture the warpage behavior of the SDBGA matrix, because the change of the centroidal moment of inertia of cross section after deformation cannot be considered due to small deformation assumption. The nonlinear large deformation analysis must be taken instead. Based on the nonlinear analysis, an advanced warpage prediction methodology for matrix SDBGA is established. This methodology is then used to characterize the warpage behavior of matrix SDBGA and to study the different effects on the warpage. Warpage of matrix SDBGA during the whole assembly processes is also predicted. For the SDBGA matrix investigated, the crossbow dominant warpage and buckling phenomena are observed for the matrix after bottom die bonding and after interposer bonding, which are new findings in the warpage study for electronic packages. It is also found that not only the total die length, but also the dice distribution will affect the warpage pattern of the matrix. For the matrix after top die bonding and after molding, normal warpage patterns are observed, i.e., both crossbow and coilset warpage are comparable. "Bending interaction" and the "warpage competition" mechanisms are proposed to explain the warpage characteristic for matrix SDBGA. View full abstract»

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  • Handheld use condition-based bend test development

    Page(s): 240 - 249
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    For handheld electronic applications such as cell phones and personal digital assistants (PDAs), repeated key strokes could result in considerable flexure of the printed circuit board (PCB) mounted inside the housing. In this study, a standardized four-point bend test, including test board design, test setup, and test input level, has been developed. The S-N curve has been obtained by plotting the reliability at all deflection levels as a function of solder joint strain energy density. The effect of test frequency has also been evaluated. The reliability model prediction of three-point bend reliability matches the experimental data extremely well. The transfer function between reliability stressing and field condition is a strain-energy-density-based power law relationship. Finite-element simulation has been conducted for the worst case cell phone subjected to key presses. The use condition data including strain profiles and frequency have been incorporated in the field life prediction. The four-point bend performance can be converted into the component reliability during cell phone field use conditions. This study establishes the correlation between the use conditions and reliability tests. The cyclic four-point bend test will be implemented in the Joint Electron Device Engineering Council (JEDEC) bend test standard for handheld components. View full abstract»

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  • A general method for the connection of a component thermal model to a board

    Page(s): 250 - 263
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    In this paper, a generalized method for the connection of a thermal component model in board- and system-level thermal simulations is presented. The method allows for the definition of uniform heat flow connections as well as the standard uniform temperature interface regions. The use of uniform heat flow ports will be shown to better handle cases where large temperature gradients are present in the base model. The two methods of connecting the component model will be evaluated using two different models. First, a simple example will be presented to illustrate the nonphysical behavior introduced by the use of uniform temperature connections. Second, a model of an electronic package will be used to evaluate the relative merits of the two connection methods with respect to board thermal conductivity and boundary conditions present on the board and the package. It will be shown that the results from use of uniform heat flow connections are generally better than from use of uniform temperature regions with respect to predicting junction and board temperatures. View full abstract»

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  • Comprehensive dynamic analysis of wirebonding on Cu/low-K wafers

    Page(s): 264 - 270
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    Comprehensive dynamic analysis is performed in this paper to simulate wirebonding on Cu/low-K wafers, which involves both the impact and the ultrasonic vibration stages. After the impact stage, the contact region between the pad and the gold ball is welded to allow subsequent ultrasonic vibrations to take place. Parametric studies are carried out to investigate structural responses of the Cu/low-K layer due to variation of the moduli of Cu/low-K components. View full abstract»

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  • Advanced acoustic microimaging using sparse signal representation for the evaluation of microelectronic packages

    Page(s): 271 - 283
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    Acoustic microimaging (AMI) has been widely used to nondestructively evaluate microelectronic packages for the presence of internal defects. To detect defects in small devices such as μBGA, flip-chip, and chip-scale packages, high acoustic frequencies are required for the conventional AMI systems. The acoustic frequency used in practice, however, is limited by its penetration through materials. In this paper, a novel acoustic microimaging technique, which utilizes nonlinear signal processing techniques to improve the resolution and robustness of conventional AMI, is proposed and investigated. The technique is based on the concept of sparse signal representations in overcomplete time-frequency dictionaries. Simulation and experimental results show its super resolution and high robustness. View full abstract»

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  • Board-level solder joint reliability analysis of thermally enhanced BGAs and LGAs

    Page(s): 284 - 290
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    Thermally enhanced ball grid arrays (BGAs) are designed to have reduced thermal resistance through features such as heat slug, heat spreader, and thermal solder joints. This paper studies the design comparison of five types of thermally enhanced BGAs, i.e., conduction cooled BGA (C2BGA), metal-core BGA, exposed-die land grid array (LGA), slug LGA, and spreader LGA. The solder joint reliability performance of thermally enhanced BGAs is benchmarked with conventional thin-profile fine-pitch ball grid array (TFBGA). Both global and local three-dimensional finite-element analysis (FEA) models are established to predict the fatigue life of solder joints during thermal cycle testing. Detailed pad design with realistic geometry of solder balls and nonlinear material properties are considered in the model. The fatigue model is based on a modified Darveaux's approach with nonlinear viscoplastic analysis of solder joints. For the test vehicles studied, the critical solder joints are located near the package corner. Design variations investigated include the effects of key package dimensions and material properties. Design variations are mainly reported using C2BGA package as the trend for the other four thermally enhanced BGAs was similar. The choice of mold compound (MC) material is critical, and a material with higher coefficient of thermal expansion (CTE1) and lower modulus is preferred. Die size, die attach, and slug-attach material have little effect on solder joint reliability. It is observed that there is good correlation of fatigue life between modeling prediction and thermal cycle testing for C2BGA. Reliability of C2BGA thermal solder joints is proven to be excellent, and heat can be effectively conducted away from the die to the PCB. This is crucial to the design of C2BGA. In addition, solder joint fatigue life is found to be related to package warpage induced during thermal cycling test. A design with less package warpage usually has a longer fatigue life. View full abstract»

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  • Direct fabrication of electric components on insulated boards by laser microcladding electronic pastes

    Page(s): 291 - 294
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    In this paper, a novel method to fabricate the electronic components directly on insulating boards such as glass, ceramics, and organic laminated boards by laser microcladding electronic pastes was reported. With computer-aided design/computer-aided manufacturing (CAD/CAM) capability, the conductive metal lines and resistors with different patterns were fabricated successfully by this technique without mask. The experimental results demonstrated that the fabricated conductive lines and resistors have the same properties as those made by conventional thick-film methods and were bonded very well with the substrate. The minimum widths of the conductive lines on ceramic board, glass board, and printed circuit board can reach 20, 40, and 80 μm, correspondingly. The maximum rates for laser microcladding can be beyond 50 mm/s. Some typical examples of circuit boards fabricated by this method were illustrated. View full abstract»

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  • A novel aluminum-filled composite dielectric for embedded passive applications

    Page(s): 295 - 306
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    This paper presents the development of a novel aluminum-filled high dielectric constant composite for embedded passive applications. Aluminum is well known as a low-cost and fast self-passivation metal. The self-passivation forms a nanoscale insulating boundary outside of the metallic spheres, which has dramatic effects on the electrical, mechanical, and chemical behaviors of the resulting composites. Influences of aluminum particle size and filler loading on the dielectric properties of composites were studied. Because of the self-passivated insulating oxide layer of fine aluminum spheres, a high loading level of aluminum can be used while the composite materials continues to be insulating. Dielectric property measurement demonstrated that, for composites containing 80 wt% 3.0 μm aluminum, a dielectric constant of 109 and a low dissipation factor of about 0.02 can be achieved. The dielectric constant of epoxy-aluminum composites increased almost 30 times as compared with that of the pure epoxy matrix, which is about 3.5. Die shear tests showed that at such loading level, materials still had good processability and good adhesion toward the substrate. Bulk resistivity measurement, high-resolution transmission electron microscope (HRTEM) observation, and thermogravimetric analysis (TGA) were conducted to characterize the aluminum powders in order to understand the dielectric behavior of aluminum-filled composites. Bimodal aluminum-filled composites were also systematically studied in order to further increase the dielectric constant. Ouchiyama-Tanaka's model was used to calculate the theoretical maximum packing fraction (MPF) of bimodal systems. Based on the calculation, rheology studies were performed to find the optimum bimodal filler volume fraction ratio that led to the best packing efficiency of bimodal fillers. It was found that the viscosity of polymer composites showed a minimum at optimum bimodal filler volume fraction ratio. A high dielectric constant of 160 (@10 kHz) with a low dissipation factor of less than 0.025 was achieved with the optimized bimodal aluminum composites. The developed aluminum composite is a promising candidate material for embedded capacitor applications. View full abstract»

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  • 50-GHz integrated interconnects in silicon optical microbench technology

    Page(s): 307 - 313
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    A custom-designed silicon-based 50-GHz interconnect is integrated for packaging demonstrations of broadband optoelectronic (OE) applications in silicon optical microbench technology. The half-shielded (or partially shielded) 0.5-cm interconnect has 25-dB isolation and 0.9-dB transmission loss over 50 GHz. When implemented in this packaged architecture, the nature of the interconnect minimizes coupling and eliminates the need for an external test fixture that is prevalent in a more conventional approach. The interconnect is further demonstrated in a multiport electrical package to illustrate the potential of this architecture up to 40-Gb data rates, and the resulting package has insertion loss less than 5 dB at 50 GHz. View full abstract»

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  • Effects of microstructural defects in multilayer LTCC stripline

    Page(s): 314 - 319
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    This paper proposes novel stripline models including embedded pores and sharpened conductor edges, which are commonly introduced during the multilayer low-temperature cofired-ceramic (LTCC) process. This model enables designers to obtain conductivity and tanδ of the stripline that are difficult to obtain using the experimental methods from arbitrary frequencies. This paper confirms that the proposed models are appropriate for LTCC striplines by comparing the simulated results with the experimental results. We found that embedded pores contributed to increase in unloaded quality factor (Qu) and characteristic impedance in the range of 5% to 6% while effective εr decreased in the range of 11%. Sharpened edges contributed to maximum peak in Qu and decreased characteristic impedance. These models will contribute to precision design of the future LTCC striplines. View full abstract»

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  • An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances

    Page(s): 320 - 334
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    Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it. Full-wave methods are often employed to study the power integrity problem. While full-wave methods can be accurate, they are time and memory consuming. The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network. However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency. A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes. Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced. Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network. While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes. Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived. This allows both frequency and transient responses to be done with SPICE simulation. View full abstract»

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  • Modeling and analyzing vertical interconnections

    Page(s): 335 - 342
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    Continual interest in miniaturization is driving electronic packaging toward three-dimensional (3-D) structures and system integration. Utilization of a third dimension allows designers much more freedom, but at the same time it leads to an increase in the complexity of signal routing. High-density of components and interconnection increases the need for electromagnetic (EM) modeling. This paper focuses on EM modeling and the analysis of vertical interconnection in a stacked 3-D package. Solder-plated polymer balls are used in vertical interconnection between interposers and laser-drilled vias through the interposers. High-frequency responses of the vertical interconnections were studied with 3-D full-wave software. Based on the EM analysis, we propose equivalent circuit models for vertical connections, which were verified with measurements. In addition, an impedance-matching technique in vertical interconnection is discussed. View full abstract»

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  • Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

    Page(s): 343 - 353
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    This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results. View full abstract»

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  • A study of dual-mode bandpass filter integrated in BGA package for single-chip RF transceivers

    Page(s): 354 - 358
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    This paper presents a study of a dual-mode bandpass filter integrated in a ball grid array (BGA) package for the single-chip solutions of radio frequency (RF) transceivers. The novel in-package filter, except for the economical advantage of mass production and automatic assembly, has potential benefit to the system-level board miniaturization and the system-level manufacturing facilitation. The simulated and measured performance of the in-package filter is presented. The effects of the different physical parts of the package on the filter performance are investigated. Experimental results show that the in-package filter of size 15×15×1.905 mm3 achieved 3-dB percentage bandwidth of 14% and insertion loss of 2.07 dB at 5.25 GHz. View full abstract»

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  • Signal integrity characterization of microwave XFP ASIC BGA package realized on low-K liquid crystal polymer (LCP) substrate

    Page(s): 359 - 363
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    With the development of low-K nanometer devices, the need for compatible packaging material is ever increasing. Liquid crystal polymer (LCP) is emerging as a promising material for RF, microwave, and millimeter-wave packaging. Its coefficient of thermal expansion can be matched to that of low-K die to ensure mechanical reliability. This paper, for the first time, characterizes the electrical performance of a wire bonded application-specific integrated circuit (ASIC) ball grid array (BGA) package based on LCP substrate technology for application in 10 Gb/s small form factor pluggable module (XFP) optical communication systems. Specifically, it compares the electrical performance of LCP to that of traditionally used FR4_epoxy (FR-4) and Polyimide (PI) substrate materials. Findings show that at 10 GHz, insertion loss was decreased as much as 31% and 15% compared to FR-4 and PI, respectively. In particular, mode conversion was decreased by 66% and 42% compared to FR-4 and PI, respectively. Time delay was decreased by 10 and 4 ps compared to FR-4 and PI. No significant differences in power, ground coupling, and simultaneously switching output (SSO) noise at 10 GHz were observed. Based on the package structure used in this study, it was concluded that LCP offers superior electrical performance compared to FR_4, PI, and is qualified as next generation substrate material for high data rate XFP BGA packaging. View full abstract»

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  • Cost-effective chip-on-heat sink leadframe package for 800-Mb/s/lead applications

    Page(s): 364 - 371
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    Chip-on-heat sink leadframe (COHS-LF) packages offer a simple, low-cost chip encapsulation structure with advanced electrical and thermal performance for high-speed integrated circuit applications. The COHS-LF package is a novel solution to the problems of increased power consumption and signal bandwidth demands that result from high-speed data transmission rates. Not only does it offer high thermal and electrical performance, but also provides a low-cost short time-to-market package solution for high-speed applications. In general, there are two main memory packages employed by the most popular high-speed applications, double data rate (DDR) SDRAM. One is the cheaper, higher parasitic leadframe packages, such as the thin small outline packages (TSOPs), and the other is the more expensive, lower parasitic substrate-based packages, such as the ball grid array (BGA). Due to the requirement for higher ambient temperature and operating frequency for high-speed devices, DDR2 SDRAM packages were switched from conventional TSOPs to more expensive chip-scale packages (i.e., BGA) with lower parasitic effects. And yet, by using an exposed heat sink pasted on the surface of the chip and packed in a conventional leadframe package, the COHS-LF is a simpler, lower cost design. Results of a three-dimensional full-wave electromagnetic field solver and SPICE simulator tests show that the COHS-LF package achieves less signal loss, propagation delay, edge rate degradation, and crosstalk than the BGA package. Furthermore, transient analysis using the wideband T-3π models optimized up to 5.6 GHz for signal speeds as high as 800 Mb/s/lead demonstrates the accuracy of the equivalent circuit model and reconfirms the superior electrical characteristics of COHS-LF package. View full abstract»

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  • 2nd Annual Organic Microelectronics Workshop (ACS/IEEE/MRS)

    Page(s): 373
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    Freely Available from IEEE
  • 15th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP 2006)

    Page(s): 374
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    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering