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IEEE Transactions on Computers

Issue 6 • June 2006

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Displaying Results 1 - 15 of 15
  • [Front cover]

    Publication Year: 2006, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2006, Page(s): c2
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  • Program counter-based prediction techniques for dynamic power management

    Publication Year: 2006, Page(s):641 - 658
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3643 KB) | HTML iconHTML

    Reducing energy consumption has become one of the major challenges in designing future computing systems. This paper proposes a novel idea of using program counters to predict I/O activities in the operating system. It presents a complete design of program-counter access predictor (PCAP) that dynamically learns the access patterns of applications and predicts when an I/O device can be shut down to... View full abstract»

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  • A hardware Gaussian noise generator using the Box-Muller method and its error analysis

    Publication Year: 2006, Page(s):659 - 671
    Cited by:  Papers (55)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2384 KB) | HTML iconHTML

    We present a hardware Gaussian noise generator based on the Box-Muller method that provides highly accurate noise samples. The noise generator can be used as a key component in a hardware-based simulation system, such as for exploring channel code behavior at very low bit error rates, as low as 10-12 to 10-13. The main novelties of this work are accurate analytical error anal... View full abstract»

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  • Reducing rename logic complexity for high-speed and low-power front-end architectures

    Publication Year: 2006, Page(s):672 - 685
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5943 KB) | HTML iconHTML

    In modern day high-performance processors, the complexity of the register rename logic grows along with the pipeline width and leads to larger renaming time delay and higher power consumption. Renaming logic in the front-end of the processor is one of the largest contributors of peak temperatures on the chip and, so, demands attention to reduce the power consumption. Further, with the advent of cl... View full abstract»

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  • An efficient dynamic algorithm for maintaining all-pairs shortest paths in stochastic networks

    Publication Year: 2006, Page(s):686 - 702
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3840 KB) | HTML iconHTML

    This paper presents a new solution to the dynamic all-pairs shortest path routing problem, using a linear reinforcement learning scheme. The particular instance of the problem that we have investigated concerns finding the all-pairs shortest paths in a stochastic graph, where there are continuous probabilistically-based updates in edge-weights. We present the details of the algorithm with an illus... View full abstract»

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  • Risk-resilient heuristics and genetic algorithms for security-assured grid job scheduling

    Publication Year: 2006, Page(s):703 - 719
    Cited by:  Papers (91)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4623 KB) | HTML iconHTML

    In scheduling a large number of user jobs for parallel execution on an open-resource grid system, the jobs are subject to system failures or delays caused by infected hardware, software vulnerability, and distrusted security policy. This paper models the risk and insecure conditions in grid job scheduling. Three risk-resilient strategies, preemptive, replication, and delay-tolerant, are developed ... View full abstract»

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  • Simple error detection methods for hardware implementation of Advanced Encryption Standard

    Publication Year: 2006, Page(s):720 - 731
    Cited by:  Papers (50)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2161 KB) | HTML iconHTML

    In order to prevent the Advanced Encryption Standard (AES) from suffering from differential fault attacks, the technique of error detection can be adopted to detect the errors during encryption or decryption and then to provide the information for taking further action, such as interrupting the AES process or redoing the process. Because errors occur within a function, it is not easy to predict th... View full abstract»

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  • A new reliability-oriented place and route algorithm for SRAM-based FPGAs

    Publication Year: 2006, Page(s):732 - 744
    Cited by:  Papers (88)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1875 KB) | HTML iconHTML

    The very high integration levels reached by VLSI technologies for SRAM-based field programmable gate arrays (FPGAs) lead to high occurrence-rate of transient faults induced by single event upsets (SEUs) in FPGAs' configuration memory. Since the configuration memory defines which circuit an SRAM-based FPGA implements, any modification induced by SEUs may dramatically change the implemented circuit.... View full abstract»

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  • On optimization of e-textile systems using redundancy and energy-aware routing

    Publication Year: 2006, Page(s):745 - 756
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2115 KB) | HTML iconHTML

    Recent advances in the electronic device manufacturing technology have opened many research opportunities in pervasive computing. Among the emerging design platforms, "electronic textiles" (or e-textiles) make possible a wide variety of novel applications, ranging from consumer electronics to aerospace devices. Due to the harsh environment of e-textile components and battery size limitations, low-... View full abstract»

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  • Toward a theory for scheduling dags in Internet-based computing

    Publication Year: 2006, Page(s):757 - 768
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1524 KB) | HTML iconHTML Multimedia Media

    Conceptual and algorithmic tools are developed as a foundation for a theory of scheduling complex computation-dags for Internet-based computing. The goal of the schedules produced is to render tasks eligible for allocation to remote clients (hence, for execution) at the maximum possible rate. This allows one to utilize remote clients well, as well as to lessen the likelihood of the "gridlock" that... View full abstract»

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  • Measuring benchmark similarity using inherent program characteristics

    Publication Year: 2006, Page(s):769 - 782
    Cited by:  Papers (50)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4075 KB) | HTML iconHTML

    This paper proposes a methodology for measuring the similarity between programs based on their inherent microarchitecture-independent characteristics, and demonstrates two applications for it: 1) finding a representative subset of programs from benchmark suites and 2) studying the evolution of four generations of SPEC CPU benchmark suites. Using the proposed methodology, we find a representative s... View full abstract»

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  • Comment on "Computing the shortest network under a fixed topology

    Publication Year: 2006, Page(s):783 - 784
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (230 KB) | HTML iconHTML

    A linear programming formulation was given for the problem of computing a shortest network under a fixed topology (under the lambda-metric). We point out a nontrivial error in this paper and give a correct and simpler linear programming formulation. We also show that the result can be generalized to any distance function given by a Minkowski unit circle that is a centrally symmetric polygon View full abstract»

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  • TC Information for authors

    Publication Year: 2006, Page(s): c3
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  • [Back cover]

    Publication Year: 2006, Page(s): c4
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org