By Topic

Computers and Digital Techniques, IEE Proceedings -

Issue 3 • Date 2 May 2006

Filter Results

Displaying Results 1 - 8 of 8
  • Editorial - Field-programmable logic and applications

    Publication Year: 2006 , Page(s): 137 - 138
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (60 KB)  

    First Page of the Article
    View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Defect tolerance in multiple-FPGA systems

    Publication Year: 2006 , Page(s): 139 - 145
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (214 KB)  

    SRAM-based field programmable gate arrays (FPGAs) have an inherent capacity for defect tolerance. A simple scheme that exploits this potential in multiple-FPGA systems is proposed. The symmetry of the system is exploited to yield a large number of possible mappings of bitstreams on FPGAs, which results in a high probability that at least one functional mapping exists. It is shown that the behaviour of a system built using a large number of defective FPGAs approaches that of the ideal defect-free system. Various interconnection topologies such as the tree, the crossbar and a hybrid form are compared. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Measuring and utilising the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks

    Publication Year: 2006 , Page(s): 146 - 156
    Cited by:  Papers (2)  |  Patents (22)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (187 KB)  

    As the logic capacity of field-programmable gate arrays (FPGAs) increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of conventional logic blocks, FPGAs can now include digital signal processors, multipliers, multi-bit addressable memory cells and even processor cores. One of the common characteristics of these new building blocks is their multi-bit design, where each block is designed specifically to process several bits of data at a time. This multi-bit processing paradigm is significantly different from the single-bit processing design of the conventional FPGA logic blocks, as it creates differentiation in signals through its bussed structures. Consequently, the correlation between the positions of the signals in buses and the connectivity of these signals is examined. On the basis of correlation measurements, a multi-bit routing architecture is then proposed along with its routing tool. It is experimentally shown that, compared with the conventional routing architectures, the multi-bit architecture requires 6-12% less area to implement. In particular, it needs 27% fewer routing switches to connect its multi-bit blocks to their routing tracks and 18% less configuration memory to store the configuration information. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modular dynamic reconfiguration in Virtex FPGAs

    Publication Year: 2006 , Page(s): 157 - 164
    Cited by:  Papers (43)  |  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (561 KB)  

    Modular systems implemented on field-programmable gate arrays (FPGAs) can benefit from being able to load and unload modules at run-time, a concept that is of much interest in the research community. Although dynamic partial reconfiguration is possible in Virtex and Spartan series FPGAs, the configuration architecture of these devices is not amenable to modular reconfiguration, a limitation which has relegated research to theoretical or compromised resource allocation models. Two methods for implementing modular reconfiguration in Virtex FPGAs are compared and contrasted. The first method offers simplicity and fast reconfiguration times, but limits the geometry and connectivity of the system. The second method, developed recently, enables modules to be allocated arbitrary areas of the FPGA, bridging the gap between theory and reality and unlocking the latent potential of dynamic reconfiguration. The cost of this advancement is increased reconfiguration time. The second method has been demonstrated in three applications, including the first reported implementation of modular reconfiguration in a Virtex-4 device. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • FPGA programmable logic block evaluation using quantified Boolean satisfiability

    Publication Year: 2006 , Page(s): 165 - 172
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    A novel field programmable gate array (FPGA) logic synthesis technique that determines if a logic function can be implemented in a given programmable circuit is presented, and how this problem can be formalised and solved using quantified Boolean satisfiability is described. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has many applications to FPGAs. The application demonstrated is the FPGA programmable logic block evaluation and the results show that this tool allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Application-specific customisation of multi-threaded soft processors

    Publication Year: 2006 , Page(s): 173 - 180
    Cited by:  Papers (8)  |  Patents (14)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    A multi-threaded microprocessor with a customisable instruction set, CUStomisable Threaded ARchitecture (CUSTARD), is proposed. CUSTARD features include design space exploration and a compiler for automatic selection of custom instructions. Custom instructions, optimised for a specific application, accelerate frequently performed computations by implementing them as dedicated hardware. Field programmable gate array implementations of CUSTARD are evaluated using media and cryptography benchmarks, and commercial MicroBlaze processor is compared. As low as 28% area overhead for four interleaved threads and up to 355% speedup over a processor without custom instructions are demonstrated. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • PNoC: a flexible circuit-switched NoC for FPGA-based systems

    Publication Year: 2006 , Page(s): 181 - 188
    Cited by:  Papers (23)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (161 KB)  

    Increases in chip density due to Moore's law allow for the implementation of ever larger and more complex systems on a single chip (SoCs). The communication mechanisms employed in such SoCs are an important contribution to their overall performance. Networks on chip (NoCs) promise to overcome the scalability problems found in bus-based interconnect. To date, most work has focused on packet-switched NoCs. Circuit-switched networks are an intriguing alternative, which promise high communication rates and predictable communication latencies. A new lightweight circuit-switched architecture called programmable NoC (PNoC) is described. PNoC is a flexible architecture that is suitable for use in FPGA-based systems. Implementation results on a Virtex-II Pro device are given using an image binarisation demonstration which resulted in as much as a 23× speedup compared with a shared bus implementation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accelerating molecular dynamics simulations with configurable circuits

    Publication Year: 2006 , Page(s): 189 - 195
    Cited by:  Papers (9)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (195 KB)  

    Molecular dynamics (MD) is of central importance to computational chemistry. Here the authors show that MD can be implemented efficiently on a commercial off-the-shelf (COTS) field programmable gate array (FPGA) board, and that speed-ups from 31× to 88× over a PC implementation can be obtained. Although the extent of speed-up depends on the stability required, 46× can be obtained with virtually no detriment, and the upper end of the range is apparently viable in many cases. The authors sketch the FPGA implementations and describe the effects of precision on the trade-off between the performance and quality of the MD simulation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.