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Computers and Digital Techniques, IEE Proceedings E

Issue 1 • Date Jan 1992

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Displaying Results 1 - 12 of 12
  • Clockless synchronisation of distributed concurrent processes

    Page(s): 88 - 92
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    For synchronising operations in a distributed computer or control system where the units are closely coupled, the three-wire synchroniser, originally developed for the 1987 IEEE Futurebus Standard, has some advantages over the use of common clock waveforms. After pointing out these advantages and reviewing the operation of the synchroniser, the paper presents a recent development in which each unit of the system can carry out several sequences of operations concurrently, the sequences being largely independent of one another. Within any unit, the different sequences will generally operate on the same set of registers, and so precautions have to be taken to prevent operations in two or more of the sequences from accessing the same register at the same time. This is done by arranging for any sequence to be able, when necessary, to cause other sequences to pause, but otherwise each of them proceeds at its own maximum speed. View full abstract»

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  • Global study on data compression techniques for digital Chinese character patterns

    Page(s): 1 - 8
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    Dot matrix representation of Chinese characters is the most popular method used, however, it requires a relatively large memory for the storage of Chinese character patterns. For the purpose of a global study, various data compression techniques are investigated to determine the method that requires the least amount of memory for data storage. The entropy of Chinese character patterns preprocessed using the two-dimensional prediction algorithm shows the best results and appears almost independent of the subblock resolutions of m*n. Therefore, a possible bound of data compression for Chinese character patterns can be predicted. The data compression technique involving two-dimensional prediction preprocessing as well as arithmetic coding for subblock symbols is found to be capable of achieving the best compression results for the 13051 Chinese character patterns with various fonts in different resolutions. View full abstract»

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  • Very-high-speed VLSI 2s-complement multiplier using signed binary digits

    Page(s): 29 - 34
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    A high-speed 8*8-bit multiplier design for 2s-complement binary numbers is presented. The multiplier uses the binary signed-digit number system to achieve both high speed and layout simplicity, and is implemented in double layer metal 2 mu m CMOS technology. The multiplication time for the array was found by simulation to be 18 ns at 25 degrees C and its size was measured as 1.7 mm*2.3 mm (excluding pads). Power dissipation was calculated as just less than 40 mW at 55 MHz, and the transistor count is 3754 transistors. View full abstract»

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  • Performance analysis of bridged LANs

    Page(s): 64 - 72
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    As the requirements of LANs have evolved, an increasing number of LANs now incorporate MAC bridges. In many instances, however, the choice of bridges, and the interconnection topologies used with them, is being made based on technological grounds rather than on firm predictions of improvements in overall network response times. The paper identifies the issues that must be considered when expanding a LAN and also, through a series of simulation results, illustrates the effect on the overall network performance of various bridge parameters and interconnection topologies. The paper concludes with some guidelines to be followed for creating a bridged LAN comprising many interconnected segments. View full abstract»

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  • FFT architecture for WSI with concurrent error detection and fault location

    Page(s): 13 - 20
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    The paper presents a new approach for concurrent error detection in homogeneous VLSI/WSI architectures for the computation of the complex N-point fast Fourier transform (FFT). The proposed approach is based on the relationship between the computations of cells at a given point distance. This relationship is analysed with respect to functional and physical faults. It is proved that a 100% probability of detection is possible. Overhead issues for hardware and timing are addressed. It is proved that hardware overhead is 50% compared to a fault intolerant complex 2-point implementation. Fault detection can be accommodated online and on a component basis (multiplier or adder/subtractor); full fault location is accomplished by a roving technique, which utilises a reconfiguration approach at no significant time overhead. The proposed technique can be accommodated efficiently in a homogeneous layout for WSI implementation. A two-phase reconfiguration policy for the proposed architecture is presented. It is proved that switching and routing overhead are modest, while achieving a significant reliability improvement over previous approaches. View full abstract»

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  • Modelling peak shapes obtained by Hough transform

    Page(s): 9 - 12
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    The paper studies peak shapes obtained when using the Hough transform. The work was motivated by the author's finding that Hough transform peaks are sometimes sharper than a priori reasoning would suggest. A mathematical model for the simple case of circle detection has been able to explain this satisfactorily, but the detailed form of the model is somewhat surprising and suggests that high peak sharpness will be a common characteristic of Hough transform peaks. View full abstract»

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  • Time characteristics of IEEE 802.4 token bus protocol

    Page(s): 81 - 87
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    Timed token protocols have increased in importance with the growth of local area network (LAN) communications One of the most important timed token protocols is certainly IEEE 802.4, a standard given the name 'token bus', which represents one of the most interesting solutions to the problem of handling, on the same physical channel, the transmission of messages belonging to multiple priority classes. In the paper, the authors study some time characteristics of the IEEE 802.4 protocol, giving bounds to the mean and the maximum duration of a complete token cycle. It is shown how these results can be conveniently used by a network designer to tune the parameters that characterise an IEEE 802.4 local area network. View full abstract»

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  • Layout optimisation for yield enhancement in on-chip-VLSI/WSI parallel processing

    Page(s): 21 - 28
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    The paper investigates the layout optimisation problem for processor-array networks. If an appropriate shape geometry is selected for the processors, a specific interconnection network can be area-efficiently mapped on a VLSI/WSI chip to maximise the chip yield, operational reliability and circuit performance. A formal technique of cellular layout by polyomino tiles is proposed, with application to mapping a variety of processor geometries onto specific array networks. The layout algorithms are expressed in a new notational language, which is amenable to cellular layout in contrast to classical procedural languages. The layout technique is illustrated with both well known parallel-processing array networks and a new fault-tolerant square mesh with reconfigurable processors and interconnect. The square mesh with redundant processors provides high yield and operational reliability. View full abstract»

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  • Correctness analysis for class of asynchronous communication mechanisms

    Page(s): 35 - 49
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1152 KB)  

    Real-time system design options increase significantly if the individual concurrent processes are able to communicate with no mutual timing interference. This requirement can be met by a particular class of asynchronous communication mechanisms for the transfer of reference data between a single writer and a single reader, which is characterised by the use of multiple shared memory locations (slots), and where access to these slots is co-ordinated by small shared control variables. Such mechanisms guarantee that the data obtained by the reader is always the most recent (freshest) to have been supplied by the writer, and that the data is valid (coherent) within some timing constraints expressed in terms of the relative rates and phases of the two processes. The data coherence and freshness properties of one, two, three and four slot mechanisms are examined by analysing the dynamically changing roles of the slots during asynchronous operation. This novel approach rigorously proves the predicted properties, and it provides a useful insight to the nature of shared memory communication under asynchronous operating conditions. View full abstract»

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  • Heuristic algorithms for register allocation

    Page(s): 73 - 80
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    A model to find the optimal register allocation of program variables, including large strongly connected regions (loops), is presented. The program is represented by a directed control flow graph and assumes that all variables have been allocated to memory locations. The model takes into account the cost and saving times involved in allocating variables to registers in each node of the program in order to maximise the global time saving in program execution. As the solution of this model requires exponential resources (both time and space) in the worse case, two heuristic algorithms with O(m) and O(m2) complexities have been developed. Comparisons between the performance of the two heuristic algorithms and the optimal one are made for a set of representative programs. View full abstract»

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  • Structured knowledge manipulation system for real-time engineering applications

    Page(s): 59 - 63
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    A structured knowledge manipulation system (SKMS), which incorporates a relational processing unit based on a structured knowledge representation, providing real-time relational accesses of a knowledge base, is described. Direct hardware support is provided for set operations and 'between bounds' matching. Additionally, 'garbage collection' is performed concurrently, with no memory overheads and very little speed penalty. Experimental results and projected performance figures are presented, which demonstrate the suitability of the SKMS approach for real-time applications. View full abstract»

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  • Fixed point model for adaptive token passing bus protocol

    Page(s): 50 - 58
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (564 KB)  

    The performance of an adaptive token passing bus protocol is analysed by modelling the behaviour of each node as an M/GI/1 queue and deriving a set of fixed point equations. The technique is shown to be applicable to the analysis of a number of variants of the token passing bus protocol which arise in communication networks and computer integrated manufacturing systems. The validity of the independence assumption underlying this approach is investigated by first examining the autocorrelation function of the simulated time series of token passing cycles. This indicates that cycles are not highly correlated except at high traffic loads. Mean message transmission times predicted by the models are compared with the corresponding results of simulation experiments and the performance of the adaptive protocol is compared quantitatively with that of the standard protocol. View full abstract»

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