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Electron Devices, IEEE Transactions on

Issue 5 • Date May 2006

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Displaying Results 1 - 25 of 52
  • [Front cover]

    Page(s): c1
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  • IEEE Transactions on Electron Devices publication information

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  • Table of contents

    Page(s): 937 - 939
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    Page(s): 940
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  • Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing

    Page(s): 944 - 964
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    Semiconductor industry has increasingly resorted to strain as a means of realizing the required node-to-node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility), and chemical (diffusion and activation) properties. As silicon is strained and subjected to high-temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained-silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design. View full abstract»

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  • Hybrid-orientation technology (HOT): opportunities and challenges

    Page(s): 965 - 978
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    At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper. View full abstract»

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  • Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs

    Page(s): 979 - 989
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    Issues surrounding the integration of Hf-based high-κ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-κ CMOSFETs with wide process latitude. HfO2 of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-κ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-κ layer. View full abstract»

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  • High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

    Page(s): 990 - 999
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    For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5× over bulk Si devices, 2× mobility enhancement and >10× BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (TGe<3 nm) very high Ge fraction (∼ 80%) channel and Si cap (TSi cap<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (TSOI=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4× over bulk Si devices, >2.5× over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5× over 60% strained SiGe (on relaxed bulk Si) devices. View full abstract»

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  • High-mobility low band-to-band-tunneling strained-Germanium double-gate heterostructure FETs: Simulations

    Page(s): 1000 - 1009
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    Large band-to-band tunneling (BTBT) leakage currents can ultimately limit the scalability of high-mobility (small-bandgap) materials. This paper presents a novel heterostructure double-gate FET (DGFET) that can significantly reduce BTBT leakage currents while retaining its high mobility, making it suitable for scaling into the sub-20-nm regime. In particular, through one-dimensional Poisson-Schrodinger, full-band Monte Carlo, and detailed BTBT simulations, the tradeoffs between carrier transport, electrostatics, and BTBT leakage in high-mobility sub-20-nm Si-strained SiGe-Si (high germanium concentration) heterostructure PMOS DGFETs are thoroughly analyzed. The results show a dramatic (>100×) reduction in BTBT and an excellent electrostatic control of the channel while maintaining very high drive currents and switching frequencies in these nanoscale transistors. View full abstract»

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  • Uniaxial-process-induced strained-Si: extending the CMOS roadmap

    Page(s): 1010 - 1020
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    This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k·p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and <110> channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be ∼ 4 times higher for uniaxial stress on (100) wafer and ∼ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer. View full abstract»

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  • Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs

    Page(s): 1021 - 1029
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    The combination of channel mobility-enhancement techniques such as strain engineering with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future technology nodes. The tradeoff between transport enhancement and OFF-state leakage current is compared experimentally for UTB MOSFETs in two types of materials: 1) strained Si directly on insulator (SSDOI) and 2) strained Si/strained Si1-zGez (z=0.46-0.55)/strained Si heterostructure-on-insulator (HOI). SSDOI of moderate strain level (e.g. ∼ 0.8%) yields high electron-mobility enhancements for all electron densities, while high strain levels (e.g. ∼ 1.6%) are required to obtain hole-mobility enhancements at high inversion charge densities. HOI is demonstrated to have similar electron-mobility characteristics to SSDOI, while hole mobilities are improved and can be maintained at high inversion charge densities. Hole mobility in strained channels with thickness below 10 nm is studied and compared for SSDOI and HOI. As the channel thickness is reduced, mobility decreases, as in unstrained silicon-on-insulator (SOI), though hole-mobility enhancements are demonstrated into the ultrathin-channel regime. Increased OFF-state leakage currents are observed in HOI compared to SSDOI and SOI. For a 4-nm-thick buried SiGe layer, leakage is reduced relative to devices with thicker SiGe channels. View full abstract»

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  • Performance enhancement of partially and fully depleted strained-SOI MOSFETs

    Page(s): 1030 - 1038
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    The authors have developed short-channel strained-silicon-on-insulator (strained-SOI) MOSFETs on silicon-germanium (SiGe)-on-insulator (SGOI) substrates fabricated by the Ge condensation technique. 35-nm-gate-length strained-SOI MOSFETs were successfully fabricated. The strain in Si channel is still maintained for the gate length of 35 nm. The performance enhancement of over 15% was obtained in 70-nm-gate-length strained-SOI n-MOSFETs. Fully depleted strained-SOI MOSFETs with back gate were successfully fabricated on SGOI substrate with SiGe layers as thin as 25 nm. The back-gate bias control successfully operated and the higher current drive was obtained by a combination of the low doping channel and the back-gate control. View full abstract»

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  • Processing aspects in the low-frequency noise of nMOSFETs on strained-silicon substrates

    Page(s): 1039 - 1047
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    The impact of different processing factors on the low-frequency (LF) noise of nMOSFETs fabricated in strained-silicon (SSi) substrates will be described. It is shown that the use of an SSi substrate can yield improved LF noise performance compared with standard Czochralski silicon material. This is demonstrated for both full-wafer and selective epitaxial SSi material. The lower 1/f noise points to an improved gate oxide quality, i.e., with a lower interface and bulk defect density, and is correlated with the low-field mobility or transconductance of the transistors. At the same time, it will be demonstrated that there exist defect-related LF noise mechanisms, which generally give rise to excess generation-recombination (GR) noise. Associated with this GR noise, a degradation of either the OFF-state leakage current or the mobility (transconductance) of the devices is observed. It is clear that noise is a sensitive parameter to local defectiveness and may be a useful tool for both materials' characterization and the analysis of processing-related device degradation mechanisms. View full abstract»

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  • Overview and status of metal S/D Schottky-barrier MOSFET technology

    Page(s): 1048 - 1058
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    In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar action. These and other benefits accrue using a low-thermal-budget CMOS manufacturing process requiring two fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials such as high-k gate insulators and strained silicon substrates. SB MOSFET technology state of the art is also reviewed, and shown to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region. SB-PMOS devices tend to have superior performance compared to NMOS, but NMOS performance has recently improved by using ytterbium silicide or by using hybrid structures that incorporate interfacial layers to lower the SB height. View full abstract»

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  • Merits of heat assist for melt laser annealing

    Page(s): 1059 - 1064
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    In this paper, the potential for sub-10-nm junction formation of partial-melt laser annealing (PMLA), which is a combination of solid-phase regrowth and heat-assisted laser annealing (HALA), is demonstrated. HALA and PMLA are effective for reducing laser-energy density for dopant activation and for improving heating uniformity of device structure. The absence of melting at the dopant profile tail for PMLA results in a negligibly small diffusion at this region. A high activation rate is achievable by melting the upper part of the amorphous-silicon layer. The obtained sheet resistance of 10-nm-deep junctions was about 700 Ω/sq. for both n+/p and p+/n junctions. These results imply that PMLA is applicable for much shallower junction formation. View full abstract»

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  • Channel hot-electron degradation on 60-nm HfO2-gated nMOSFET DC and RF performances

    Page(s): 1065 - 1072
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    Channel hot-carrier-induced dc and RF performance degradations in 60-nm high-k nMOSFETs are examined experimentally. RF performances such as the cutoff frequency, noise figure, linearity, and flicker noise of high-k MOSFETs show significant vulnerability to the hot-electron effect. Analytical equations for normalized RF degradations relating to the device dc and ac parameters are derived. Good agreement between the analytical predictions and experimental data is obtained. The accuracy of the model equations suggests fast and effective evaluation of noise figure and linearity degradations using simple dc and ac parameters directly. View full abstract»

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  • A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs-from single electron emission to PBTI recovery transient

    Page(s): 1073 - 1079
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    A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large- and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method. View full abstract»

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  • Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

    Page(s): 1080 - 1087
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    Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from -50 to 200°C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical <110> pillar sidewalls and the horizontal <100> wafer surface. View full abstract»

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  • Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization

    Page(s): 1088 - 1095
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    Multiple-gate devices, such as the planar double-gate (DG), triple-gate (TG), FinFET, Pi-Gate (PG), and Omega-Gate Silicon-on-Insulator (SOI) MOSFETs are potential candidates for achieving the performance targets of the International Roadmap of the Semiconductor Industry Association. In this paper, wideband experimental and three-dimensional simulation analyses have been carried out to compare the analog/RF performance of DG, TG/FinFET, PG, and single-gate (SG) SOI MOSFETs. The characteristics of the multiple-gate devices were analyzed in the dc and ac regimes from subthreshold region to strong inversion and saturation regions. In both regimes, the advantages and limitations of the multiple-gate devices over the SG structure are discussed for channel length scaling well below 100 nm. To the authors' knowledge, it is the first time that such extensive results and analyses are presented on the potential of these novel devices for high-frequency analog applications. View full abstract»

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  • Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT ∼ 1 nm) SiO2 and high-κ gate stacks

    Page(s): 1096 - 1106
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    Building on a previously presented compact gate capacitance (Cg-Vg) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (Ig-Vg) is provided for both ultrathin SiO2 and high-dielectric constant (high-κ) gate stacks of equivalent oxide thickness (EOT) down to ∼ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact Cg-Vg model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schrödinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO2 and high-κ/SiO2 gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO2, Si3N4, and high-κ (e.g., HfO2) gate stacks on (100) Si with EOTs down to ∼ 1-nm show excellent agreement. View full abstract»

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  • Cascaded quantum wires and integrated designs for complex logic functions: nanoelectronic full adder

    Page(s): 1107 - 1111
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    Complex logic functions based on cascading quantum wires (QWs) defined in a GaAs/AlGaAs-based two-dimensional electron gas by electron-beam lithography and wet chemical etching are demonstrated. The concept of connected QWs leads to a nanoelectronic full adder with independent carry- and sum-bit structures. Monolithic designs were fabricated and were found to also demonstrate simultaneous switching with common thresholds between high and low logic levels. View full abstract»

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  • Study on discharge stability of cost-effective driving method based on Vt close-curve analysis in AC plasma-display panel

    Page(s): 1112 - 1119
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    A new cost-effective driving method that can drive plasma-display panel cells without applying any driving waveform to the common electrode is proposed based on a Vt close-curve analysis. In this driving method, it is very important to prevent a misfiring discharge due to the inversion of the polarity of the wall charges accumulated between the scan and address electrodes. The measured Vt close-curve showed that a misfiring discharge caused by the polarity inversion phenomenon of the wall charges on the scan and address electrode could be prevented by minimizing the potential difference between the scan and address electrodes by applying a positive auxiliary pulse to the address electrode, especially while applying the positive sustain pulse during a sustain period. As a result, the proposed cost-effective driving method can reduce the driving cost by about 20% through eliminating the common driving board and successfully display various image patterns, such as the white, red, green, and blue patterns, on a 42-in plasma television without any misfiring discharge. View full abstract»

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  • Theory of interface-trap-induced NBTI degradation for reduced cross section MOSFETs

    Page(s): 1120 - 1130
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    Negative Bias Temperature Instability (NBTI)-induced degradation for ultra-scaled and future-generation MOSFETs is investigated. Numerical simulations based on Reaction-Diffusion framework are implemented. Geometric dependence of degradation arising from the transistor structure and scaling is incorporated into the model. The simulations are applied to narrow-width planar triple-gate and surround-gate MOSFET geometries to estimate the NBTI reliability under several scaling scenarios. Unless the operating voltages are optimized for specific geometry of transistor cross section, the results imply worsened NBTI reliability for the future-generation devices based on the geometric interpretation of the NBTI degradation. A time-efficient and straightforward analysis is developed to predict the degradation. This compact model confirms the numerical simulations. View full abstract»

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  • Quantum-mechanical effects in trigate SOI MOSFETs

    Page(s): 1131 - 1136
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    A self-consistent Poisson-Schrödinger solver is used to calculate the current in trigate n-channel silicon-on-insulator transistors with sections down to 2 nm × 2 nm. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device is reduced and as the electron concentration in the channel is increased. As a consequence, the threshold voltage is higher than predicted by classical Poisson solvers. The current drive is diminished, and the subthreshold slope is degraded, especially in the devices with the smallest cross sections. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology