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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • May 2006

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Displaying Results 1 - 25 of 29
  • Table of contents

    Publication Year: 2006, Page(s):c1 - c4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2006, Page(s): c2
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  • Guest Editorial

    Publication Year: 2006, Page(s):741 - 742
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  • Using simulation and satisfiability to compute flexibilities in Boolean networks

    Publication Year: 2006, Page(s):743 - 755
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    Simulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (S&S) can be tightly integrated to efficiently compute flexibilities in a multilevel Boolean network, including the following: 1) complete "don't cares" (CDCs); 2) sets of pairs of functions to be distinguished (SPFDs); and 3) sets of candidate n... View full abstract»

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  • Hardware compilation of application-specific memory-access interconnect

    Publication Year: 2006, Page(s):756 - 771
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB) | HTML iconHTML

    A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integrated circuit systems is the presence of memory accesses to a shared-memory subsystem. The latency to access memory is often not statically predictable, which creates problems for scheduling operations dependent on memory reads. More fundamental is that dependences between accesses may not be static... View full abstract»

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  • Optimal register sharing for high-level synthesis of SSA form programs

    Publication Year: 2006, Page(s):772 - 779
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    Register sharing for high-level synthesis of programs represented in static single assignment (SSA) form is proven to have a polynomial-time solution. Register sharing is modeled as a graph-coloring problem. Although graph coloring is NP-Complete in the general case, an interference graph constructed for a program in SSA form probably belongs to the class of chordal graphs that have an optimal O(|... View full abstract»

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  • On partitioning and symbolic model checking

    Publication Year: 2006, Page(s):780 - 788
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    State-space-partitioning-based approaches have been proposed in the literature to address the state-explosion problem in model checking. These approaches, whether sequential or distributed, perform a large amount of work in the form of interpartition (crossover) image computations, which can be expensive. A model-checking algorithm that aggregates these expensive crossover images by localizing com... View full abstract»

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  • Analysis and synthesis of weighted-sum functions

    Publication Year: 2006, Page(s):789 - 796
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    A weighted-sum (WS) function computes the sum of selected integers. This paper considers a design method for WS functions by look-up table (LUT) cascades. In particular, it derives upper bounds on the column multiplicities of decomposition charts for WS functions. From these, the size of LUT cascades that realize WS functions can be estimated. The arithmetic decomposition of a WS function is also ... View full abstract»

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  • Comparison of two designs for the multifunction vehicle bus

    Publication Year: 2006, Page(s):797 - 805
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    In this paper, two designs for the decoder of the multifunction vehicle bus (MVB) are compared. The first one follows a bottom-up methodology and the second one has been created in a top-down style. Although this latter methodology is more systematic and easy to automate, it results in a lower performance. In the case of the MVB decoder, the ratio of bottom-up performance to the top-down one range... View full abstract»

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  • Hierarchical synthesis of complex DSP functions using IRIS

    Publication Year: 2006, Page(s):806 - 820
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1336 KB) | HTML iconHTML

    A "white box" design methodology, which deals with hierarchical synthesis issues by providing a bridge between a high-level algorithm representation and lower level design tools, is presented. It illustrates tradeoffs when dealing with designs in a hierarchical and flattened manner. An enhanced Minnesota architectural synthesis scheduling algorithm is given, which gives highly efficient field prog... View full abstract»

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  • Formal derivation of optimal active shielding for low-power on-chip buses

    Publication Year: 2006, Page(s):821 - 836
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB) | HTML iconHTML

    Passive shielding has been used to reduce the capacitive coupling effects of adjacent bus lines by inserting passive ground or power lines (shields) between them. Active shielding is another shielding technique in which the shield is allowed to switch depending on the switching pattern of its adjacent bus lines. This paper formally derives the optimal active shielding logic function for minimum po... View full abstract»

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  • High-level current macro model for logic blocks

    Publication Year: 2006, Page(s):837 - 855
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB) | HTML iconHTML

    The authors present a frequency domain current macro-modeling technique for capturing the dependence of the block current waveform on its input vectors. The macro model is based on estimating the discrete cosine transform (DCT) of the current waveform and then taking the inverse transform to estimate the time domain current waveform. The DCT of a current waveform is very regular and closely resemb... View full abstract»

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  • Module relocation to obtain feasible constrained floorplans

    Publication Year: 2006, Page(s):856 - 866
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    This paper considers the general problem of relocating modules to convert infeasible constrained floorplanner inputs into feasible ones. This is accomplished by placing modules in locations that attempt to minimize the standard deviation of module densities. Efficient geometric algorithms are developed and shown to be successful in obtaining feasible inputs. Experimental results examine the tradeo... View full abstract»

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  • Design-specific path delay testing in lookup-table-based FPGAs

    Publication Year: 2006, Page(s):867 - 877
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    Due to the increased use of field-programmable gate arrays (FPGAs) in production circuits with high reliability requirements, the design-specific testing of FPGAs has become an important topic for research. Path delay testing of FPGAs is especially important since path delay faults can render an otherwise fault-free FPGA unusable for a given design layout. This paper presents a new approach for FP... View full abstract»

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  • Concurrent detection of erroneous responses in linear analog circuits

    Publication Year: 2006, Page(s):878 - 891
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    This paper presents a novel methodology for concurrent error detection in linear analog circuits. The error-detection circuit monitors the input and some observable internal nodes of the examined circuit and generates an estimate of its output. The estimate coincides with the output in error-free operation, while in the presence of errors, it diverges. Thus, concurrent error detection is performed... View full abstract»

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  • Modeling and analysis of crosstalk noise in coupled RLC interconnects

    Publication Year: 2006, Page(s):892 - 901
    Cited by:  Papers (72)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    At current operating frequencies, inductive-coupling effects can be significant and should be included for accurate crosstalk-noise analysis. In this paper, an analytical framework to model crosstalk noise in coupled RLC interconnects is presented. The proposed model is based on transmission-line theory and captures high-frequency effects in on-chip interconnects. The new model is generic in natur... View full abstract»

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  • Effect of improved lower bounds in dynamic BDD reordering

    Publication Year: 2006, Page(s):902 - 909
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    In this paper, we present new lower bounds on binary decision diagram (BDD) size. These lower bounds are derived from more general lower bounds that recently were given in the context of exact BDD minimization. The results presented in this paper are twofold. First, we gain deeper insight by looking at the theory behind the new lower bounds. Examples lead to a better understanding, showing that th... View full abstract»

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  • SPICE-based mixed-mode S-parameter calculations for four-port and three-port circuits

    Publication Year: 2006, Page(s):909 - 913
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    Mixed-mode s-parameters assist in the design and characterization of four-port and three-port differential RF/microwave circuits. A new method for extracting mixed-mode s-parameters for four-port and three-port circuits modeled with SPICE is presented in which the s-parameters are extracted from node voltages. This method is efficient for circuits that are designed in SPICE and is free from any as... View full abstract»

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  • Increasing encoding efficiency of LFSR reseeding-based test compression

    Publication Year: 2006, Page(s):913 - 917
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    A new methodology to increase the encoding efficiency of test compression based on linear feedback shift registers (LFSRs) is proposed. The proposed method combines LFSR reseeding and bit fixing. Deterministic test patterns tend to have a biased probability of the logic value 1 or 0 at each primary input. If such biased inputs are fixed to the logic value 1 or 0 with some combinational logic, then... View full abstract»

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  • Practical repeater insertion for low power: what repeater library do we need?

    Publication Year: 2006, Page(s):917 - 924
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    This paper investigates the problem of repeater insertion for low power under a given timing budget. A novel repeater insertion algorithm is proposed to compute the optimal repeater number and width in the discrete solution space, as defined by a given repeater library. Using the proposed algorithm, two practical and highly important questions are addressed. Given a certain tolerance to the degrad... View full abstract»

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  • Analyzing continuous-time ΔΣ Modulators with generic behavioral models

    Publication Year: 2006, Page(s):924 - 932
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB) | HTML iconHTML

    In a generic behavioral model of an analog or mixed-signal electronic system, the internal and external signals and their interactions are formulated by more general descriptions than in commonly used behavioral models. This allows a more flexible design methodology. Whereas a behavioral model models an architecture of a system at a specific abstraction level, a generic behavioral model is built u... View full abstract»

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  • An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs

    Publication Year: 2006, Page(s):932 - 938
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    This paper presents an error control method for application of the discrete cosine transform (DCT) to extraction of substrate parasitics in integrated circuits. In addition to the truncation error with approximating an infinite series with a finite number of terms, there are also errors in approximating the truncated series by the DCT. It is shown that this error is important for accurate parasiti... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2006, Page(s): 939
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  • IEEE Biomedical Circuits and Systems Conference healthcare technology (BiOCAS 2006)

    Publication Year: 2006, Page(s): 940
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  • Special issue on nanoelectronic circuits and nanoarchitectures

    Publication Year: 2006, Page(s): 941
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu