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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 2006

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Displaying Results 1 - 25 of 31
  • [Front cover]

    Page(s): c1 - c4
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    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits publication information

    Page(s): c2
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    Freely Available from IEEE
  • Table of contents

    Page(s): 1001 - 1002
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  • New Associate Editor

    Page(s): 1003
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    Freely Available from IEEE
  • High-speed circuit designs for transmitters in broadband data links

    Page(s): 1004 - 1015
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1904 KB) |  | HTML iconHTML  

    Various high-speed techniques including internal peaking, differentially stacked inductor, and dual-loop PLL for wireline communications are proposed,analyzed, and verified by means of three independent circuits. A multiplexer incorporates multiple peaking techniques and gate control switching to achieve an operation speed of 20 Gb/s while consuming 22 mW from a 1.8-V supply. A voltage-controlled oscillator employing differentially stacked inductor accomplishes a phase noise of -90dBc/Hzat 1-MHz offset with a minimum power of 1 mW. A clock multiplication unit utilizes dual-loop architecture as well as a third-order loop filter, arriving at an output jitter of 0.2 ps, rms (0.87 ps, rms de-embedding 0.84 ps, rms from the instruments) and 4.5 ps, pp while consuming 40 mW from a 1.8-V supply. View full abstract»

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  • Fast acquisition clock and data recovery circuit with low jitter

    Page(s): 1016 - 1024
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    This paper presents a half-rate clock and data recovery circuit (CDR)that combines the fast acquisition of a phase selection (PS) delay-locked loop (DLL) with the low jitter of a phase-locked loop (PLL). The PLL acquisition time improves considerably with use of a phase frequency magnitude detector(PFMD) that feeds back an estimate of the magnitude of the frequency difference in addition to the sign. Measurements in 0.5μm CMOS technology show operation up to 700 Mb/s, a 7% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps after the PLL acquires lock. With a phase frequency detector (PFD), the PLL locks in about 700 ns from an initial frequency difference of 7%. Measurements using a PFMD show the 700 ns PLL acquisition time is reduced on average by about a factor of 5 to 140 ns from an initial 7% frequency difference. The power dissipation is 300mW. View full abstract»

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  • 10-Gb/s modulator drivers with local feedback networks

    Page(s): 1025 - 1030
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    A novel intrinsic collector-base capacitance (CCB) feedback network (ICBCFN) was incorporated into the conventional cascode and series-connected voltage balancing (SCVB) circuit configurations to implement 10-Gb/s modulator drivers. The drivers fabricated in 0.35-μm SiGe BiCMOS process could generate 9 VPP differential output swings with rise/fall time of less than 29 ps. Also, the ICBCFN was modified as an intrinsic drain-gate capacitance feedback network (IDGCFN) to implement drivers with differential output swing of 8 VPP in 0.18-μm CMOS process. The power consumption is as low as 0.6 W. The present work shows that the driving capability is greater than that of the currently reported silicon-based drivers. View full abstract»

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  • Self-calibrated quadrature generator for WLAN multistandard frequency synthesizer

    Page(s): 1031 - 1041
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    A self-calibrated quadrature generator capable of generating local oscillator (LO) outputs for IEEE 802.11a-b is presented. The quadrature generator is embedded in a frequency synthesizer that generates reference frequencies at 2.4 and 5GHz. A new sequential calibration scheme maintains the quadrature at the 5-GHz output within a maximum phase error of 2°, while a divide-by-two flip-flop generates the quadrature output at 2.4 GHz. The circuit is fabricated in a 0.25-μm SiGe BiCMOS technology and occupies a silicon area of 2 mm2; the quadrature generator consumes a current of 5 mA from a 2.5-V supply. View full abstract»

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  • A fully integrated V-band PLL MMIC using 0.15-μm GaAs pHEMT technology

    Page(s): 1042 - 1050
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    A fully integrated V-band phase-locked loop (PLL) MMIC with good phase noise and low-power consumption is developed using 0.15-μm GaAs pHEMTs. For V-band frequency division,a wideband divide-by-3 frequency divider is proposed using cascode FET-based harmonic injection locking. The fourth subharmonic mixer using anti-parallel diode pair is employed as a high-frequency phase detector. In this way, the required frequency of the reference oscillator is lowered to one twelfth of V-band output signal. An RC low-pass filter and DC amplifier are also integrated to effectively suppress the spurious and harmonic signals, and to increase the loop gain. To reduce the circuit interactions and frequency pulling effect, buffer amplifiers are used at the output of VCO and frequency divider. The fabricated V-band PLL MMIC shows the locking range of 840 MHz around 60.1GHz under a very low power dissipation of 370 mW. Good phase noise of -95.5 dBc/Hz is measured at 100 kHz offset. The chip size is as small as 2.35×1.80 mm2. To the best of our knowledge, the PLL MMIC of this work is one of the highest frequency monolithic PLLs that integrates all the required elements on a single chip. View full abstract»

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  • A 0.7-2-GHz self-calibrated multiphase delay-locked loop

    Page(s): 1051 - 1061
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    A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks in the proposed DLL can be self-calibrated. When the calibration procedure is finished, the digital calibration circuit can be turned off automatically to save power dissipations and reduce noise generations. A start controlled circuit is proposed to enlarge the operating frequency range of the DLL. Both the start-controlled circuit and the calibration circuit require an external reset signal to ensure the correctness of the calibration after temperature,operating frequency, and power supply voltage are settled. This DLL with the digital calibration circuit has been fabricated in a 0.18-μm CMOS process. The measured results show the DLL exhibits a lock range of 0.7-2 GHz while the peak-to-peak jitter and rms jitter is 18.9ps and 2.5 ps at 2 GHz, respectively. When the calibration procedure is completed and the DLL operates at 1 GHz, the maximum mismatch-induced timing error among multiphase clocks is reduced from 20.4 ps (7.34 degree) to 3.5 ps (1.26 degree). View full abstract»

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  • A simple on-chip repetitive sampling setup for the quantification of substrate noise

    Page(s): 1062 - 1072
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    The quantification of substrate noise is an important issue in mixed-signal designs, where sensitive analog circuits are embedded in a hostile digital environment. In this paper we present an experimental environment to characterize the sensitivity of embedded analog circuits to digitally generated substrate noise. Our measurement technique is based on equivalent-time substrate voltage sampling and uses a simple differential latch comparator without explicit input sample-and-hold. A surprisingly large measurement bandwidth is observed,which is explained from the detailed circuit behavior. On our 0.18-μm CMOS test chip,we have demonstrated that our system allows to wave trace pulses as narrow as 200 ps accurately. Additionally, the extraction of precise measurement data from observations that are excessively corrupted by additive noise and timing jitter is addressed. We present simple yet very effective methods to accurately reconstruct pulse waveform features without the use of delicate deconvolution operations. View full abstract»

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  • Highly linear 0.18-μm CMOS power amplifier with deep n-Well structure

    Page(s): 1073 - 1080
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    The linearity of a 0.18-μm CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (Cgs), which is the dominant nonlinear source, and partially from drain junction capacitance (Cjd). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-μm standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of Pout, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P1dB. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of Pout, 18.9 dB of power gain and 35% of PAE at P1dB. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results. View full abstract»

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  • A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

    Page(s): 1081 - 1091
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    A 36 mm/sup 2/ graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-/spl mu/m 6-metal standard CMOS logic process. View full abstract»

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  • Constant-ratio-coupled multi-grain digital synchronizer with flexible input-output delay selection for versatility in low-power applications

    Page(s): 1092 - 1099
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    The constant-ratio-coupled multi-grain digital synchronizer (CRC-MGsynchronizer) is proposed as a means for making high-speed connections with very low power consumption, both among multiple chips such as processors, controllers, and storage devices, and among on-chip modules. The synchronizer not only provides a wide range of operating frequencies, but is fast locking and only occupies a small area on chip. Therefore, it contributes to large reductions in power consumption and costs. It is suitable for use in various low-power systems (e.g., battery-hungry mobile appliances and low-cost consumer electronic products). Three major techniques were applied to the design: 1)a multi-grain structure for the delay elements, which greatly reduces the number of gates while facilitating locking in a very small number of clock cycles;2) constant-ratio-coupled (CRC) delay lines (measurement versus generation)for flexible selection of the input-output delay; and 3) a new lock stage decision circuit (LSDC) scheme, conferring excellent testability. Moreover,the architecture is all-digital, and thus it has high process portability. By applying these techniques to a DDR memory interface circuit for a mobile application processor fabricated in 130-nm technology, we were able to reduce power consumption by 42% and chip area by 65% compared with a conventional implementation. Furthermore, the novel design spans a frequency range covering 12 times the minimum frequency. View full abstract»

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  • Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

    Page(s): 1100 - 1107
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    A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-μm 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices. View full abstract»

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  • An AND-type match-line scheme for high-performance energy-efficient content addressable memories

    Page(s): 1108 - 1119
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    High search speed and low energy per search are two major design goals of content-addressable memories (CAMs). In this paper, an AND-type match-line scheme is proposed to realize a high-performance energy-efficient CAM. The realized 256 × 128-b CAM macro, based on a 0.18-μm 1.8-V CMOS process, achieves a 2.1-ns search time. When both the stored and search data are generated from an on-chip 4 × 32-b LFSR with the same seed, the measured energy is 2.33-fJ/bit/search. View full abstract»

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  • Introduction to the Special Section on the 2005 IEEE RFIC Symposium

    Page(s): 1120 - 1121
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  • A single-chip tri-band (2100, 1900, 850/800 MHz) WCDMA/HSDPA cellular transceiver

    Page(s): 1122 - 1132
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    This paper describes the design and performance of the first tri-band (2100, 1900, 800/850 MHz) single-chip 3G cellular transceiver IC for worldwide use. The transceiver has been designed to meet all narrowband blocker, newly proposed Adjacent Channel II, and Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The design is part of a reconfigurable reference platform for multi-band, multi-mode (GSM/EDGE + WCDMA) radios. The zero-IF receiver is comprised of a novel multi-band quadrature mixer, seventh-order baseband filtering, and a novel DC offset correction scheme, which exhibits no settling time or peak switching transients after gain steps. The receiver lineup is designed to optimize HSDPA throughput and minimize sensitivity to analog baseband filter bandwidth variations. The direct-launch transmitter is made up of a third-order baseband filter, an I/Q modulator with variable gain, an integrated transformer, an RF variable gain amplifier, and a power amplifier driver. At +9.5-dBm output power, the transmitter achieves an error vector magnitude (EVM) of 4%. Fractional-N synthesizers achieve fast lock times of 50 μs (150 μs) within 20 ppm (0.1 ppm). Automatically calibrated, integrated VCOs achieve a 1.6-GHz tuning range to facilitate coverage over all six 3GPP frequency bands. The IC draws 34 mA in receive (18-mA receiver plus 16-mA fractional-N PLL/VCO) and 50 to 62 mA in transmit (-76 dBm to +9.5 dBm), including PLL/VCO, using a 2.775-V supply voltage. The RF transceiver is integrated with the baseband signal processing and associated passives in a 165-pad package, resulting in the first tri-band 3G radio transceiver with a digital interface which requires no external components. View full abstract»

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  • A quad-band 8PSK/GMSK polar transceiver

    Page(s): 1133 - 1141
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    The addition of 8PSK modulation to the GSM standard creates the need for architectural modifications to achieve necessary performance while maintaining a cost-effective solution. A large-signal polar modulation transmitter allows the use of an efficient nonlinear power amplifier (PA) for both GMSK and 8PSK. Digital interfaces are used for both receiver and transmitter, with analog options available for compatibility with older technology baseband systems. The receiver section of the transceiver is programmable to operate in direct conversion mode or multiple VLIF modes. All analog and digital filtering necessary to define the final channel is included. The transmit section of the transceiver uses an all digital system with a fractional-N digital modulator for the phase path. The amplitude path uses a Powerstar PA with both the ramp and the amplitude modulation applied to the collector. The transceiver meets or exceeds all specifications for both GMSK and 8PSK in all four cellular bands (850/900/1800/1900). View full abstract»

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  • A new transponder architecture with on-chip ADC for long-range telemetry applications

    Page(s): 1142 - 1148
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    We present a new architecture for wireless power and data telemetry that recovers power and a system clock from a weak incident RF signal. A high-efficiency RF-DC converter generates a 3-VDC supply for the system from a -12.3-dBm incident RF signal, gathered by a commercial 50-Ω antenna. A system clock is extracted from the same incident signal, by an injection-locked LC oscillator. Sub-harmonic injection-locking facilitates the separation of the incident and the transmit signal frequencies, without need for a PLL. The proposed architecture is used in a long-range telemetry device, incorporating an on-chip ADC, and employing active telemetry for data transmission. Data is transmitted through binary phase-shift-keying of a 900-MHz carrier. The prototype, implemented in 0.25-μm CMOS, occupies less than 1 mm2. A wireless operation range of more than 18 meters is indicated by anechoic chamber testing. View full abstract»

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  • A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

    Page(s): 1149 - 1159
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    A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm2. View full abstract»

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  • A digitally controlled oscillator system for SAW-less transmitters in cellular handsets

    Page(s): 1160 - 1170
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    A complete digitally controlled oscillator (DCO) system for mobile phones is presented with a comprehensive study. The DCO is part of a single-chip fully compliant quad-band GSM transceiver realized in a 90-nm digital CMOS process. By operating the DCO at a 4 × GSM low-band frequency followed by frequency dividers, the requirement of on-chip inductor Q and the amount of gate oxide stress are relaxed. It was found that a dynamic divider is needed for stringent TX output phase noise while a source-coupled-logic divider can be used for RX to save power. Both dividers are capable of producing a tight relation between four quadrature output phases at low voltage and low power. Frequency tuning is achieved through digital control of the varactors which serve as an RF DAC. Combining a MIM capacitor array and two nMOS transistor arrays of the varactors for the RF DAC, a highly linear oscillator gain which is also insensitive to process shift is achieved. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. With a sigma-delta dithering, high frequency resolution is obtained while having negligible phase noise degradation. The measured phase noise of -167 dBc/Hz at 20 MHz offset from 915 MHz carrier and frequency tuning range of 24.5% proves that this DCO system can be used in SAW-less quad-band transmitters for mobile phones. View full abstract»

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  • An integrated LMS adaptive filter of TX leakage for CDMA receiver front ends

    Page(s): 1171 - 1182
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    The theory and practical implementation of a continuous-time LMS adaptive filter of the TX leakage in CDMA receivers are described. The filter works by injecting a matched out-of-phase copy of the TX leakage into the LNA output. It requires a reference signal coupled from the TX chain, whose I and Q components are appropriately scaled to generate the matched copy. The scale factors are the results of the correlation between the filter output signal and the I/Q components of the reference signal. The filter was designed as part of a 0.25-μm CMOS cellular-band receiver. The effect of the DC offsets in the correlators on the TX leakage rejection ratio (TXRR) was minimized by using the sign-data variant of the LMS algorithm and by increasing the gain of the correlating multipliers. The loop stability margin was improved by swapping the I and Q reference inputs of the scaling multipliers. Without a significant group delay of the TX leakage relative to the reference signal, the filter achieved the maximum TXRR of 28 dB, which was limited by the reference signal coupling. The group delay introduced by the SAW duplexer reduced the minimum TXRR to 10.8 dB. The filter degraded the LNA noise factor and gain by 1.3 dB and 1.7 dB, respectively. View full abstract»

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  • Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits

    Page(s): 1183 - 1200
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    This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 Ω·cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-μm SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply. View full abstract»

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  • Characterization, design, modeling, and model validation of silicon-wafer M:N balun components under matched and unmatched conditions

    Page(s): 1201 - 1209
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    In this paper, we characterize and model M:N baluns for silicon RFIC design. A modeling methodology is presented based on a geometrically scalable lumped-element approach that incorporates both skin effect and substrate loss. This approach is extended to include the effects of a patterned ground shield under the balun. The modeling approach is validated with measured S-parameters and extracted impedances from various circuit configurations. The impedance transfer characteristics of the model and balun over substrate and over a patterned ground shield are explored. Matching considerations are addressed by evaluating the model accuracy with measured data under matched and unmatched conditions. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan