By Topic

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 3 • Date March 2006

Filter Results

Displaying Results 1 - 15 of 15
  • Table of contents

    Page(s): c1
    Save to Project icon | Request Permissions | PDF file iconPDF (38 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Page(s): c2
    Save to Project icon | Request Permissions | PDF file iconPDF (35 KB)  
    Freely Available from IEEE
  • Decoupling capacitors for multi-voltage power distribution systems

    Page(s): 217 - 228
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB) |  | HTML iconHTML  

    Multiple power supply voltages are often used in modern high-performance ICs, such as microprocessors, to decrease power consumption without affecting circuit speed. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy. The system of decoupling capacitors used in power distribution systems with multiple power supplies is described in this paper. The noise at one power supply can propagate to the other power supply, causing power and signal integrity problems in the overall system. With the introduction of a second power supply, therefore, the interaction between the two power distribution networks should be considered. The dependence of the impedance and magnitude of the voltage transfer function on the parameters of the power distribution system is investigated. An antiresonance phenomenon is intuitively explained in this paper. It is shown that the magnitude of the voltage transfer function is strongly dependent on the parasitic inductance of the decoupling capacitors, decreasing with smaller inductance. Design techniques to cancel and shift antiresonant spikes out of range of the operating frequencies are presented. It is also shown that it is highly desirable to maintain the effective series inductance of the decoupling capacitors as low as possible to decrease the overshoots of the response of the dual-voltage power distribution system over a wide range of operating frequencies. A criterion for an overshoot-free voltage response is presented in this paper. It is noted that the frequency range of the overshoot-free voltage response can be traded off with the magnitude of the response. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine

    Page(s): 229 - 240
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1218 KB) |  | HTML iconHTML  

    A fully digital, self-adjusting, and high-efficiency power supply system has been developed based on a finite-state machine (FSM) control scheme. The system dynamically monitors circuit performance with a delay line and provides a substantially constant minimum supply voltage for digital processors to properly operate at a given frequency. In addition, the system adjusts the supply voltage to the required minimum under different process, voltage, and temperature and load conditions. The design issues of the fully digital power delivery system are discussed and addressed. This digital FSM scheme significantly reduces the complexity of control-loop implementation (<1800 gates) and power consumption (< 100 /spl mu/W at 1.2 V) compared to other approaches based on proportional-integral-differential control. The power delivery control system is fabricated in a 0.13-/spl mu/m CMOS process and its core die size is 160 /spl times/ 110 /spl mu/m/sup 2/. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • FABSYN: floorplan-aware bus architecture synthesis

    Page(s): 241 - 253
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2559 KB) |  | HTML iconHTML  

    As system-on-chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this paper, we address this problem by proposing an automated approach for floorplan-aware bus architecture synthesis (FABSYN) to synthesize cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. Our synthesis approach incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect bus cycle time violations early in the design How, at the system level. We present case studies of network communication SoC subsystems for which we synthesized bus architectures, detected and eliminated timing violations, and generated core placements in a matter of hours instead of several days for a manual effort. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth

    Page(s): 254 - 267
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2493 KB) |  | HTML iconHTML  

    Texture mapping is one of the techniques that express realism in three-dimensional (3-D) graphics. To produce high-quality images, various anisotropic filtering methods have been proposed for texture mapping. These methods require more texels than isotropic (trilinear) filtering method. In spite of increases to texture memory bandwidth, however, texture memory bandwidth is still a bottleneck of texture-filtering hardware. Consequently, an exact filtering method is required for good-quality images in a limited texture memory bandwidth. In this paper, we propose anisotropic texture filtering based on edge functions. Our method proposes an exact footprint-shape approximation with edge functions for generating weights. For real-time filtering, the weight plays a key role in effective filtering of the restricted texels loaded from memory. The normalized value of the edge function gives the distance relative to the contribution of texels to a final intensity. Calculating a Gaussian filter using this normalized value, generates a good weight. The quality of rendered images is superior to other anisotropic filtering methods with the same restricted number of texels. For images of the same quality, our method requires less than half the texels of other methods. Consequently, the improvement in performance is more than twice that of other methods. With low hardware overheads, our method can be implemented at a reasonable cost. In practice, the algorithm is demonstrated through VLSI implementation. The hardware, which is described by verilog and synthesized with a 0.35-/spl mu/m 3.3-V standard cell library, is operated at 100 MHz and it generates 100 M texture-filtered RGB pixel-color values per second. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A nonredundant ternary CAM circuit for network search engines

    Page(s): 268 - 278
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1793 KB)  

    An optimized Ternary CAM concept is introduced for the hardware search engines in high-speed Internet routers. Our design employs w + 1 RAM bits to store a word of size w, whereas a conventional TCAM needs 2w RAM bits for the same word size. Based on this concept an 8-bit cluster is designed out of 9 SRAM bits, used as the basic building block of our Prefix-CAM (PCAM) structure. Four such clusters merge to store a 32-bit IPv4 prefix, thus, configuring a PCAM suitable for Internet packet forwarding. This PCAM module employs 48% less SRAM cells and a total of 22% less transistors plus 50% less address decode interconnects compared to a conventional TCAM, for equal storage size and equal functionality. We show that PCAM can be employed for multifield packet classification. Other factors, such as lookup speed and power dissipation, are not adversely affected. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck

    Page(s): 279 - 291
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (807 KB) |  | HTML iconHTML  

    Memory latency has always been a major issue in embedded systems that execute memory-intensive applications. This is even more true as the gap between processor and memory speed continues to grow. Hardware and software prefetching have been shown to be effective in tolerating the large memory latencies inherit in large off-chip memories; however, both types of prefetching have their shortcomings. Hardware schemes are more complex and require extra circuitry to compute data access strides, while software schemes generate prefetch instructions, which if not computed carefully may hamper performance. On the other hand, some applications domains (such as multimedia) have a uniform and known a priori memory access pattern, that if exploited, could yield significant application performance improvement. With this characteristic in mind, we present our findings on hiding memory latency using the direct memory access (DMA) mode, which is present in all modern systems, combined with a software prefetch mechanism, and a customized on-chip memory hierarchy mapping. Compared to previous approaches, we are able to estimate the performance and power metrics, without actually implementing the embedded system. Experimental results on nine well known multimedia and imaging applications prove the efficiency of our technique. Finally, we verify the performance estimations by implementing and simulating the algorithms on the TI C6201 processor. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test infrastructure design for mixed-signal SOCs with wrapped analog cores

    Page(s): 292 - 304
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (687 KB) |  | HTML iconHTML  

    Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System-on-chip test scheduling with reconfigurable core wrappers

    Page(s): 305 - 309
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (253 KB) |  | HTML iconHTML  

    The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm that produces an optimal solution in linear time (O(n); n is the number of tests). We also show that the problem can be solved without preemption, and we extend the algorithm to handle: 1) test conflicts due to interconnection tests and 2) cases when the test time of a core limits an optimal usage of the TAM. The overhead in logic is given by the number of configurations, and we show that the upper-bound is three configurations per core. We compare the proposed approach with the existing technique and show, in comparison, that our technique is 2% less from lower bound. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Special section on system on chip integration

    Page(s): 310
    Save to Project icon | Request Permissions | PDF file iconPDF (462 KB)  
    Freely Available from IEEE
  • Special section on configurable computing design

    Page(s): 311
    Save to Project icon | Request Permissions | PDF file iconPDF (125 KB)  
    Freely Available from IEEE
  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Page(s): 312
    Save to Project icon | Request Permissions | PDF file iconPDF (504 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Page(s): c3
    Save to Project icon | Request Permissions | PDF file iconPDF (25 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Page(s): c4
    Save to Project icon | Request Permissions | PDF file iconPDF (29 KB)  
    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Yehea Ismail
CND Director
American University of Cairo and Zewail City of Science and Technology
New Cairo, Egypt
y.ismail@aucegypt.edu