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Micro, IEEE

Issue 2 • Date March-April 2006

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Displaying Results 1 - 18 of 18
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • [Inside front cover]

    Page(s): c2
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    Freely Available from IEEE
  • [Advertisement]

    Page(s): 1
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    Freely Available from IEEE
  • Table of contents

    Page(s): 2 - 3
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    Freely Available from IEEE
  • Masthead

    Page(s): 4
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    Freely Available from IEEE
  • Workload characterization: A key aspect of microarchitecture design

    Page(s): 5 - 6
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    Freely Available from IEEE
  • Andy's acceleration and Moore's momentum

    Page(s): 7 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (461 KB)  

    Most advances in integrated circuit manufacturing and design result from the efforts of some of the most clever engineers and scientists on the planet. Yet, that is not the whole story of economic progress. Advances in the technical frontier do not find their way into users' hands without deliberate actions by the managers of the firms who sell chips. That last observation seems uncontroversial until we consider that ephemeral economy-wide business conditions and strategic priorities shape these managers actions. Ephemeral business conditions induced a large manufacturer in a key position to attempt to get better products into user hands faster. Those types of business conditions arise only once or twice in a lifetime View full abstract»

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  • Guest Editors' Introduction: Hot Chips 17

    Page(s): 8 - 9
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    Freely Available from IEEE
  • Synergistic Processing in Cell's Multicore Architecture

    Page(s): 10 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (510 KB)  

    Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism. The streamlined architecture provides an efficient multithreaded execution environment for both scalar and SIMD threads and represents a reaffirmation of the RISC principles of combining leading edge architecture and compiler optimizations. These design decisions have enabled the Cell BE to deliver unprecedented supercomputer-class compute power for consumer applications View full abstract»

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  • Xbox 360 System Architecture

    Page(s): 25 - 37
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    This article covers the Xbox 360's high-level technical requirements, a short system overview, and details of the CPU and the GPU. The Xbox 360 contains an aggressive hardware architecture and implementation targeted at game console workloads. The core silicon implements the product designers' goal of providing game developers a hardware platform to implement their next-generation game ambitions. The core chips include the standard conceptual blocks of CPU, graphics processing unit (GPU), memory, and I/O. Each of these components and their interconnections are customized to provide a user-friendly game console product. The authors describe their architectural trade-offs and summarize the system's software programming support View full abstract»

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  • Digitally Assisted Analog Circuits

    Page(s): 38 - 47
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    Today's interfaces between digital and "real world" analog signals rely mainly on complex analog circuit components that strictly limit achievable power efficiency and throughput. Digitally assisted analog circuits can exploit digital circuits' high density and low energy per computation to enable a new generation of interface electronics based on minimal-precision, low-complexity analog building blocks View full abstract»

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  • An Extreme Processor for an Extreme Experiment

    Page(s): 48 - 57
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    Particle physics experiments stretch processing requirements to the limit, requiring the selection of extremely rare events at tens of terabytes per second. A network of 283,392 mixed-signal MIMD processors operating in parallel at 17 tbytes/s help physicists interpret data from the world's largest particle accelerator. Particle physics and heavy-ion experiments demand greater integration and fast on-detector signal processing. We believe TRD is the first system to implement complete signal digitizing, filtering, intelligent trigger processing and readout in a single on-detector chip that avoids system noise. TRD uses multiport memories as register file inputs, multiported GRFs, and a global multiport data memory. These components support high-end multiprocessing requirements under tight latency conditions. Multi-ported memories, in particular, make it possible to couple independent data streams' very efficiently. So far, the requirements for this detector have remained largely stable. The main change was to add digital filters relatively late in the design. Of course, the first weeks of measuring actual collisions at unprecedented LHC energies are the true test of our design View full abstract»

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  • CMOS Photonics for High-Speed Interconnects

    Page(s): 58 - 66
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    Luxtera has demonstrated the technology required to implement CMOS photonics, and product development is underway. It has also demonstrated all the technology required for 10-Gbps operation, in addition to that required to scale to 100 Gbps and 1 Tbps. A single 10-Gbps channel today integrates tens of optical components into a single die alongside circuitry of modest gate count, 100,000 per transceiver. For the first time, high-speed optical communications directly between silicon die are possible at a price-performance point competitive with traditional electrical interconnects View full abstract»

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  • IEEE Computer Society Information

    Page(s): 67
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  • Leakage Power Analysis and Reduction for Nanoscale Circuits

    Page(s): 68 - 80
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    Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems View full abstract»

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  • The best patents of all

    Page(s): 84
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    The author defined the most useful patent as the one whose principal element appears as an essential element in more publications than any other patent. The author found three close contenders after an extensive literature search. The top two patents address different aspects of a common substance, and the third includes a novel use of conceptual redundancy. For legal reasons, the author has been advised not to name these patents directly, but you can easily find all of them by searching the obvious keywords View full abstract»

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  • [Back inside cover]

    Page(s): c3
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  • [Back cover]

    Page(s): c4
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Aims & Scope

High-quality technical articles from designers, systems integrators, and users discussing the design, performance, or application of microcomputer and microprocessor systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center