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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 4 • Date April 2006

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  • Table of contents

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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

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  • Output regulation of discrete-time piecewise-linear systems with application to controlling chaos

    Page(s): 249 - 253
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    This paper presents an approach to output regulation of discrete-time piecewise-linear systems. A sufficient condition to guarantee output regulation of such systems via state feedback has been obtained based on piecewise-quadratic Lyapunov functions. It is shown that the output regulation controller can be obtained by solving a set of linear-matrix inequalities. Application to controlling chaos is also given to illustrate the performance of the proposed approach. View full abstract»

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  • Evolutionary design of 2-dimensional recursive filters via the computer language GENETICA

    Page(s): 254 - 258
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB) |  | HTML iconHTML  

    In this paper, we present a new design method for a class of two-dimensional (2-D) recursive digital filters using an evolutionary computational system. The design of the 2-D filter is reduced to a constrained minimization problem the solution of which is achieved by the convergence of an appropriate evolutionary algorithm. In our approach, the genotypes of potential solutions have a uniform probability within the region of the search space specified by the constraints and zero probability outside this region. This approach is particularly effective as the evolutionary search considers only those potential solutions that respect the constraints. We use the computer language GENETICA, which provides the expressive power necessary to get an accurate problem formulation and supports an adjustable evolutionary computational system. Results of this procedure are illustrated by a numerical example, and compared with those of some previous designs. View full abstract»

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  • New object-oriented segmentation algorithm based on the CNN paradigm

    Page(s): 259 - 263
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (744 KB) |  | HTML iconHTML  

    This paper illustrates a new object-oriented segmentation algorithm based on the cellular neural network (CNN) paradigm. The approach, which exploits rigorous model of the image contours, presents two remarkable features: 1) it provides more accurate segmented objects than the ones obtained by other CNN-based techniques; 2) it makes use of CNN templates that take into account the hardware characteristics imposed by the CNNUM. Results carried out for benchmark video sequences highlight the capabilities of the proposed technique. View full abstract»

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  • Probabilistic optimization for FPGA board level routing problems

    Page(s): 264 - 268
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    Field programmable gate arrays (FPGAs) are an enabling technology in circuit designs. We consider the board-level multi-terminal net assignment in the FPGA-based logic emulation. A novel probabilistic optimization method is devised for solving the net assignment problem. The approach incorporates randomized rounding, genetic algorithm, and solution-improvement strategies. Experimental results demonstrate promising performance. View full abstract»

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  • A CMOS single-chip wireless solution with an adaptive purity-control scheme against ISM-band interferences

    Page(s): 269 - 273
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB) |  | HTML iconHTML  

    The authors present a Bluetooth (BT) single-chip solution to improve the immunity to ISM-band interferences. A transceiver with a purity-controllable local oscillator is proposed. The purity control scheme is experimentally verified through the firmware which controls the interference-transfer function and adjusts the allowable interference level adaptively. This solution is fully integrated in a 0.25-μm CMOS process, and it satisfies the specification of the BT v1.2, with the optimal power consumption and the yield enhancement. View full abstract»

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  • The Δ2-conjecture for L(2,1)-labelings is true for direct and strong products of graphs

    Page(s): 274 - 277
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    A variation of the channel-assignment problem is naturally modeled by L(2,1)-labelings of graphs. An L(2,1)-labeling of a graph G is an assignment of labels from {0,1,...,λ} to the vertices of G such that vertices at distance two get different labels and adjacent vertices get labels that are at least two apart and the λ-number λ(G) of G is the minimum value λ such that G admits an L(2,1)-labeling. The Δ2-conjecture asserts that for any graph G its λ-number is at most the square of its largest degree. In this paper it is shown that the conjecture holds for graphs that are direct or strong products of nontrivial graphs. Explicit labelings of such graphs are also constructed. View full abstract»

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  • An analog-to-digital converter with Golomb-Rice output codes

    Page(s): 278 - 282
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    An analog-to-digital converter with data compression capabilities is described. By sharing circuits between an integrating converter and a Golomb-Rice encoder it is possible to jointly perform the tasks of quantization and coding. The Golomb-Rice codes are generated during the conversion cycle by employing a shift register and a digital multiplexer. The final codeword is read out serially from the shift register. The converter can also work in a noncompressing mode. This design provides a compact circuit suitable for on-sensor compression. Simulations at the system and transistor level corroborate the validity of the design. View full abstract»

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  • Highly linear programmable balanced current scaling technique in moderate inversion

    Page(s): 283 - 285
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    A technique to achieve highly linear current scaling in CMOS technologies is proposed. It is based on two balanced electronically programmable current mirrors operating in moderate inversion. The scaling factor can be continuously adjusted in a wide range. This technique can be employed to achieve or to extend gain adjustment in amplifiers. As an application example, a variable-gain differential current amplifier and a tunable transconductor are presented. Measurement results of the transconductor implemented in a 0.5-μm CMOS technology validate in silicon the proposed approach. View full abstract»

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  • A new proof of the colored branch Theorem

    Page(s): 286 - 288
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    The colored branch theorem is a result from graph theory that has been described first by Minty. It states the existence of certain meshes and cuts in a graph, whose edges are colored red, green and blue, respectively. The theorem, sometimes also referred to as the lemma of the colored arcs, can be utilized to give short and elegant proofs of many other theorems in graph and circuit theory and has therefore turned out to be of vital importance. We present a new set theoretic proof of the colored branch theorem, that reveals its relationship to the orthogonality theorem, another well-known fundamental result about meshes and cuts in a graph. View full abstract»

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  • New low-voltage class AB/AB CMOS op amp with rail-to-rail input/output swing

    Page(s): 289 - 293
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB) |  | HTML iconHTML  

    A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two VGS drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-μm CMOS technology verify the scheme operating with ±0.9-V supplies and close to rail-to-rail input and output swing. View full abstract»

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  • A voltage-mode PWM buck regulator with end-point prediction

    Page(s): 294 - 298
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB) |  | HTML iconHTML  

    The end-point prediction (EPP) scheme for voltage-mode buck regulators is proposed. Internal nodal voltages of the regulator controller are predicted and set automatically by the proposed algorithms and circuits. The settling time of the regulator can therefore be significantly reduced for faster dynamic responses, even with dominant-pole compensation. Proven experimentally by a voltage-mode buck regulator implemented in a 0.35-μm CMOS technology, the reference-tracking speed using the EPP scheme is faster than the conventional buck regulator by about six times. View full abstract»

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  • A background timing-skew calibration technique for time-interleaved analog-to-digital converters

    Page(s): 299 - 303
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    This paper presents a background timing-skew calibration technique for time-interleaved analog-to-digital converters (ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by counting the number of zero crossings of the ADCs input while randomly alternating their sampling sequence. Digitally controlled delay units are adjusted to minimize the timing skews among the A/D channels caused by the mismatches among the clock routes. The calibration behaviors, including converging speed and timing jitter, are theoretically analyzed and verified with simulations. A 6-bit 16-channel ADC is used as an example. View full abstract»

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  • Memory-efficient architecture for JPEG 2000 coprocessor with large tile image

    Page(s): 304 - 308
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    The experimental results show that using a larger tile size to perform JPEG 2000 coding results in better image quality (i.e., greater than or equal to 256 /spl times/ 256 tile image). However, processing large tile images also requires relatively high memory for the hardware implementation. For example, it would require tile memory of 256 K words to support the process of a 512 /spl times/ 512 tile image in the straightforward architecture. To reduce hardware resources, we have proposed the quad code-block (QCB) -based discrete wavelet transform method to reduce the size of tile memory by a factor of 4. In this paper, the remaining 1/4 tile memory can be further reduced through two approaches: the zero-holding extension with slight image degradation and the QCB-block size extension without any image degradation. That is, it only requires 12 K words tile memory to support the process of 512 /spl times/ 512 tile image by using zero-holding extension, and 13.58 K words memory through QCB-block size extension. The low memory requirement makes the on-chip memory practicable. View full abstract»

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  • Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design

    Page(s): 309 - 313
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    With system-on-chip design, IP blocks form routing obstacles that deteriorate global interconnect delay. In this paper, we present a new approach for obstacle-avoiding rectilinear minimal delay Steiner tree (OARMDST) construction. We formalize the solving of minimum delay tree through the concept of an extended minimization function, and trade the objective into a top-down recursion, which wisely produces delay minimization from source to critical sinks. We analyze the topology generation with treatment of obstacles and exploit the connection flexibilities. To our knowledge, this is the first in-depth study of OARMDST problem based on topological construction. Experimental results are given to demonstrate the efficiency of the algorithm. View full abstract»

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  • Double-sampling single-loop ΣΔ modulator topologies for broad-band applications

    Page(s): 314 - 318
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB) |  | HTML iconHTML  

    This paper presents novel double sampling high-order single loop sigma-delta modulator structures for wide-band applications. To alleviate the quantization noise folding into the inband frequency region, two previously reported techniques are used. The digital-to-analog converter's sampling paths are implemented with the single-capacitor approach and an additional zero is placed at the half of the sampling frequency of the modulator's noise transfer function (NTF). The detrimental effect of this additional zero on both the NTF and signal transfer function is also resolved through the proposed modulator architectures with a low additional circuit requirement. View full abstract»

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  • A high efficiency, soft switching DC-DC converter with adaptive current-ripple control for portable applications

    Page(s): 319 - 323
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    A novel control scheme for improving the power efficiency of low-voltage dc-dc converters for battery-powered, portable applications is presented. In such applications, light-load efficiency is crucial for extending battery life, since mobile devices operate in stand-by mode for most of the time. The proposed technique adaptively reduces the inductor current ripple with decreasing load current while soft switching the converter to also reduce switching losses, thereby significantly improving light-load efficiency and therefore extending the operation life of battery-powered devices. A load-dependent, mode-hopping strategy is employed to maintain high efficiency over a wide load range. Hysteretic (sliding-mode) control with user programmable hysteresis is implemented to adaptively regulate the current ripple and therefore optimize conduction and switching losses. Experimental results show that for a 1-A, 5- to 1.8-V buck regulator, the proposed technique achieved 5% power efficiency improvement (from 72% to 77%) at 100 mA of load current and a 1.5% improvement (from 84% to 85.5%) at 300 mA, which constitute light-load efficiency improvements, when compared to the best reported, state-of-the-art techniques. As a result, the battery life in a typical digital signal processing microprocessor application is improved by 7%, which demonstrates the effectiveness of the proposed solution. View full abstract»

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  • Nano-Net 2006: 1st International Conference on Nano-Networks

    Page(s): 324
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  • Special issue on nanoelectronic circuits and nanoarchitectures

    Page(s): 325
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  • IEEE Biomedical Circuits and Systems Conference healthcare technology (BiOCAS 2006)

    Page(s): 326
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  • 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2006)

    Page(s): 327
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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Page(s): 328
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  • IEEE Circuits and Systems Society Information

    Page(s): c3
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope