By Topic

Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 4 • Date April 2006

Filter Results

Displaying Results 1 - 25 of 27
  • Table of contents

    Page(s): c1 - c4
    Save to Project icon | Request Permissions | PDF file iconPDF (96 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): c2
    Save to Project icon | Request Permissions | PDF file iconPDF (35 KB)  
    Freely Available from IEEE
  • Design methodology for the optimization of transformer-loaded RF circuits

    Page(s): 761 - 768
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1152 KB)  

    In this paper, a design methodology for the optimization of transformer-loaded RF circuits is presented. The optimization procedure is based on a novel figure of merit for the integrated transformer (namely the transformer characteristic resistance), which was introduced to quantify its performance when operated as a tuned load. Using the proposed approach, a highly linear up-converter for 5-GHz wireless LAN applications was implemented in a 45-GHz-fT SiGe HBT technology. The circuit achieved an output 1-dB compression point of 4.5 dBm and a power gain of 18 dB, while drawing only 34 mA from a 3-V power supply. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Single Ping-multiple measurements: sonar bearing angle estimation using spatiotemporal frequency filters

    Page(s): 769 - 783
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB) |  | HTML iconHTML  

    Presented is a mixed-signal full-custom VLSI chip designed to receive sonar return signals from an ultrasonic microphone array, and extract input bearing angles of the incoming signals. Processing utilizes simple low-power analog spatiotemporal bandpass filters to extract wavefront velocity across the array, which translates to input bearing angle. Processing uses phase information of array signals, not onset or offset of ultrasonic burst. With such synchronous processing, multiple angle readings from different returns of the same ultrasonic transmit burst are possible. Compatible microphone arrays are compact in size-test array has a total baseline of 26.5 mm. In a test with ultrasonic beacon 65 cm from a microphone array, angular precision of 1° was demonstrated in most instances in the range -60° to 60°. Applications include sonar localization of remote objects, sonar imaging, and improved interference rejection between objects within the field of view of the sensor microphones. The chip was fabricated on a standard 3M2P CMOS process with a 0.5-μm feature size. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • RFI-induced distortion in switched-capacitor circuits

    Page(s): 784 - 794
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB) |  | HTML iconHTML  

    The errors which are induced by radio-frequency interference (RFI) in switched-capacitor (SC) circuits are discussed and the main role played by the distortion of MOS switches in the on-state is highlighted. Furthermore, a new simple analytical model, which enables one to predict RFI-induced errors in SC circuits is proposed and it is validated by the comparison of its predictions with time-domain computer simulation results. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters

    Page(s): 795 - 801
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB) |  | HTML iconHTML  

    This paper presents a partially switched-opamp technique for a high-speed, low-power pipelined analog-to-digital converter (ADC). Unlike a conventional switched-opamp technique, only the second stage of a two-stage opamp is switched with the enhanced power efficiency and the drawbacks of an opamp sharing technique and a conventional switched-opamp technique are addressed. The prototype of 8-bit 200-MS/s pipelined ADC is implemented in a 0.18-μm CMOS process technology. This converter achieves 55.8-dB spurious free dynamic range, 47.3-dB signal-to-noise-plus-distortion ratio, 7.68 effective number of bits for a 90-MHz input at full sampling rate, and consumes 30-mW from a 1.8-V supply. The active area of the ADC is 0.15 mm2. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the design of high-performance wide-band continuous-time sigma-delta converters using numerical optimization

    Page(s): 802 - 810
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    Continuous-time (CT) sigma-delta (ΣΔ) modulators are growing increasingly popular in wide-band analog-digital conversion. High orders of quantization noise shaping, and multibit quantizers, are used to compensate for the low oversampling ratios in wide-band applications. These, however, add circuit complexities and excess loop delay that are detrimental to the ΣΔ control loop. This paper presents an exact mathematical analysis technique, based on the CT-discrete time equivalence, that can take these effects into account. A design-by-optimization approach based on that analysis is used to compensate for these effects, avoid intractability issues and to gain flexibility in the design. It is also shown that it is advantageous not to fix the position of the quantization noise-shaping zeros in the signal band. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A CMOS 140-mW fourth-order continuous-time low-pass filter stabilized with a class AB common-mode feedback operating at 550 MHz

    Page(s): 811 - 820
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (856 KB)  

    A 550-MHz linear-phase low-pass continuous-time filter is described. The operational transconductance amplifier (OTA) is based on complementary differential pairs in order to achieve high-frequency operation. A common-mode feedback (CMFB) based on a Class AB amplifier with improved stability at high frequencies is introduced. Results for the stand alone OTA show a unity gain frequency of 1 GHz while the excess phase is less than 5°. The filter is based on Gm-C biquads and achieves IM3 <-40 dB for a two-tone input signal of -10 dBm each. The power consumption of the fourth-order filter is 140 mW from supply voltages of ±1.65 V. The chip was fabricated in a standard 0.35-μm CMOS technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Differential current-mode tunable wave active filters based on single-ended wave port terminators

    Page(s): 821 - 828
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB) |  | HTML iconHTML  

    A method for the design of differential current-mode wave active filters, which is based on the use of single-ended wave port terminators, is presented in this paper. The resulting filters are modular and very simple to design while their cutoff frequency is controlled by a dc current, giving them the ability of frequency tuning. As an example a wide-band bandpass filter is realized by cascading a low-pass and a highpass filter. The overall filter has been integrated using a standard 0.35-μm CMOS technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-voltage CMOS circuits for analog iterative decoders

    Page(s): 829 - 841
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1120 KB) |  | HTML iconHTML  

    Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit

    Page(s): 842 - 847
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1424 KB) |  | HTML iconHTML  

    A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-μm CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 231-1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10-12. The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel compression and encryption scheme using variable model arithmetic coding and coupled chaotic system

    Page(s): 848 - 857
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB) |  | HTML iconHTML  

    Past research in the field of cryptography has not given much consideration to arithmetic coding as a feasible encryption technique, with studies proving compression-specific arithmetic coding to be largely unsuitable for encryption. Nevertheless, adaptive modeling, which offers a huge model, variable in structure, and as completely as possible a function of the entire text that has been transmitted since the time the model was initialized, is a suitable candidate for a possible encryption-compression combine. The focus of the work presented in this paper has been to incorporate recent results of chaos theory, proven to be cryptographically secure, into arithmetic coding, to devise a convenient method to make the structure of the model unpredictable and variable in nature, and yet to retain, as far as is possible, statistical harmony, so that compression is possible. A chaos-based adaptive arithmetic coding-encryption technique has been designed, developed and tested and its implementation has been discussed. For typical text files, the proposed encoder gives compression between 67.5% and 70.5%, the zeroth-order compression suffering by about 6% due to encryption, and is not susceptible to previously carried out attacks on arithmetic coding algorithms. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Properties and experimental results of fastest linearly independent ternary arithmetic transforms

    Page(s): 858 - 866
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    Two categories of fastest linearly independent ternary arithmetic transforms, which possesses forward and inverse butterfly diagrams with the lowest computational complexity have been identified and their various properties have been presented in this paper. This family is recursively defined and has consistent formulas relating forward and inverse transform matrices. Computational costs of the calculation for new transforms are also discussed. Some experimental results for standard ternary benchmark functions and comparison with multi-polarity ternary arithmetic transform are also presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

    Page(s): 867 - 878
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (912 KB) |  | HTML iconHTML  

    Scaling down to deep submicrometer (DSM) technology has made noise a metric of equal importance as compared to power, speed, and area. Smaller feature size, lower supply voltage, and higher frequency are some of the characteristics for DSM circuits that make them more vulnerable to noise. New designs and circuit techniques are required in order to achieve robustness in presence of noise. Novel methodologies for designing energy-efficient noise-tolerant exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with good signal integrity and driving capability are proposed. The circuits designed, after applying the proposed methodologies, are characterized and compared with previously published circuits for reliability, speed and energy efficiency. To test the driving capability of the proposed circuits, they are embedded in an existing 5-2 compressor design. The average noise threshold energy (ANTE) is used for quantifying the noise immunity of the proposed circuits. Simulation results show that, compared with the best available circuit in literature, the proposed circuits exhibit better noise-immunity, lower power-delay product (PDP) and good driving capability. All of the proposed circuits prove to be faster and successfully work at all ranges of supply voltage starting from 3.3 V down to 0.6 V. The savings in the PDP range from 94% to 21% for the given supply voltage range respectively and the average improvement in the ANTE is 2.67X. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Model-order reduction using variational balanced truncation with spectral shaping

    Page(s): 879 - 891
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    This paper presents a spectrally weighted balanced truncation (SBT) technique for tightly coupled integrated circuit interconnects, when the interconnect circuit parameters change as a result of statistical variations in the manufacturing process. The salient features of this algorithm are the inclusion of the parameter variation in the RLCK interconnect, the guaranteed passivity of the reduced transfer function, and the availability of provable spectrally weighted error bounds for the reduced-order system. This paper shows that the variational balanced truncation technique produces reduced systems that accurately follow the time- and frequency-domain responses of the original system when variations in the circuit parameters are taken into consideration. Experimental results show that the new variational SBT attains, in average, 30% more accuracy than the variational Krylov-subspace-based model-order reduction techniques. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder

    Page(s): 892 - 904
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB) |  | HTML iconHTML  

    With the superior error correction capability, low-density parity-check (LDPC) codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. In the past, various structures of single code-rate LDPC decoders have been reported. However, to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC decoders that can operate at both high and low code rates are desirable. In this paper, a 9-k code length multi-rate LDPC decoder architecture is presented and implemented on a Xilinx field-programmable gate array device. Using pin selection, three operating modes, namely, the irregular 1/2 code mode, the regular 5/8 code mode, and the regular 7/8 code mode, are supported. Furthermore, to suppress the error floor level, a characterization on the conditions for short cycles in a LDPC code matrix expanded from a small base matrix is presented, and a cycle elimination algorithm is developed to detect and break such short cycles. The effectiveness of the cycle elimination algorithm has been verified by both simulation and hardware measurements, which show that the error floor is suppressed to a much lower level without incurring any performance penalty. The implemented decoder is tested in an experimental LDPC orthogonal frequency division multiplexing system and achieves the superior measured performance of block error rate below 10-7 at signal-to-noise ratio of 1.8 dB. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multidimensional vector radix FHT algorithms

    Page(s): 905 - 917
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (968 KB) |  | HTML iconHTML  

    In this paper, efficient multidimensional (M-D) vector radix (VR) decimation-in-frequency and decimation-in-time fast Hartley transform (FHT) algorithms are derived for computing the discrete Hartley transform (DHT) of any dimension using an appropriate index mapping and the Kronecker product. The proposed algorithms are more effective and highly suitable for hardware and software implementations compared to all existing M-D FHT algorithms that are derived for the computation of the DHT of any dimension. The butterflies of the proposed algorithms are based on simple closed-form expressions that allow easy implementations of these algorithms for any dimension. In addition, the proposed algorithms possess properties such as high regularity, simplicity and in-place computation that are highly desirable for software and hardware implementations, especially for the M-D applications. A close relationship between the M-D VR complex-valued fast Fourier transform algorithms and the proposed M-D VR FHT algorithms is established. This type of relationship is of great significance for software and hardware implementations of the algorithms, since it is shown that because of this relationship and the fact that the DHT is an alternative to the discrete Fourier transform (DFT) for real data, a single module with a little or no modification can be used to carry out the forward and inverse M-D DFTs for real- or complex-valued data and M-D DHTs. Thus, the same module (with a little or no modification) can be used to cover all domains of applications that involve the DFTs or DHTs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A generalized approach to the design of multiple resonance networks

    Page(s): 918 - 927
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB) |  | HTML iconHTML  

    This paper presents a simple design procedure for several types of "multiple resonance networks". These networks are LC structures, possibly including transformers, that have the property of transferring all the energy stored in a capacitor or inductor, or possibly a set of them, to another set of these elements at other part of the network, through a linear transient. A design procedure based on network synthesis is described, that allows the generation of these networks with several different structures and properties, without the need of solving a system of equations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Stability test of multidimensional discrete-time systems via sum-of-squares decomposition

    Page(s): 928 - 936
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB) |  | HTML iconHTML  

    A new stability test for d-dimensional discrete-time systems is presented. It consists of maximizing the minimum eigenvalue of a positive definite Gram matrix associated with a polynomial positive on the unit d-circle. This formulation is based on expressing the polynomial as a sum-of-squares and leads to a semidefinite programming (SDP) problem. Several heuristics are introduced for reducing the complexity of the problem in the case of sparse polynomials. Although in its practical form the test is based on a sufficient condition, the experimental results show that correct stability decisions are given. Comparisons with previous methods are favorable. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Revisiting spurious-free dynamic range of communication receivers

    Page(s): 937 - 943
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    The spurious free dynamic range (SFDR) is commonly used as a measure of dynamic range for the radio frequency and microwave front-end receivers. Although well defined in narrow-band systems, the definition becomes less clear in wide-band systems, when the nonlinearity is memoryless and the the noise figure is frequency dependent. To generalize the SFDR to wide-band systems, a meaningful physical interpretation of the conventional two-tone test is first developed. Based on this interpretation, the upper bound of the wide-band SFDR is obtained by applying a multitone test, while the lower bound is computed using the effective noise figure. The multitone test in both the memoryless and memory nonlinear Volterra systems is considered. A practical measurement technique to characterize the Volterra kernel is also provided. A realistic example based on a low noise amplifier shows a significant difference between the conventional and wide-band SFDR values. In this example, our results suggest that the use of two tones widely separated in frequency to model the interferers provides sufficiently accurate results compared to a multitone approximation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Complete stability of cellular neural networks with time-varying delays

    Page(s): 944 - 955
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    In this paper, the complete stability of cellular neural networks with time-varying delays is analyzed using the induction method and the contraction mapping principle. Delay-dependent and delay-independent conditions are obtained for locally stable equilibrium points to be located anywhere, which differ from the existing results on complete stability where the existence of equilibrium points in the saturation region is necessary for complete stability and locally stable equilibrium points can be in the saturation region only. In addition, some existing stability results in the literature are special cases of a new result herein. Simulation results are also discussed by use of two illustrative examples. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Full text access may be available. Click article title to sign in or learn about subscription options.
  • Special issue on nanoelectronic circuits and nanoarchitectures

    Page(s): 957
    Save to Project icon | Request Permissions | PDF file iconPDF (169 KB)  
    Freely Available from IEEE
  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Page(s): 958
    Save to Project icon | Request Permissions | PDF file iconPDF (504 KB)  
    Freely Available from IEEE
  • IEEE Biomedical Circuits and Systems Conference healthcare technology (BiOCAS 2006)

    Page(s): 959
    Save to Project icon | Request Permissions | PDF file iconPDF (517 KB)  
    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras