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Design & Test of Computers, IEEE

Issue 2 • Date March-April 2006

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Displaying Results 1 - 25 of 28
  • [Front cover]

    Publication Year: 2006 , Page(s): c1
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  • [Inside front cover]

    Publication Year: 2006 , Page(s): c2
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  • Call for Papers

    Publication Year: 2006 , Page(s): 81
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  • Table of contents

    Publication Year: 2006 , Page(s): 82 - 83
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  • Masthead

    Publication Year: 2006 , Page(s): 84
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  • Dealing with early life failures

    Publication Year: 2006 , Page(s): 85
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  • Guest Editor's Introduction: Evolving Methods for Detecting and Handling Reliability Defects

    Publication Year: 2006 , Page(s): 86 - 87
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    Guest editor Phil Nigh introduces the Special Issue on Latent-Defect Screening as he explores the difficulties of current methods and calls for new solutions. View full abstract»

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  • Reducing burn-in time through high-voltage stress test and Weibull statistical analysis

    Publication Year: 2006 , Page(s): 88 - 98
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB) |  | HTML iconHTML  

    To guarantee an industry standard of reliability in ICs, manufacturers incorporate special testing techniques into the circuit manufacturing process. For most electronic devices, the specific reliability required is quite high, often producing a lifespan of several years. Testing such devices for reliability under normal operating conditions would require a very long period of time to gather the data necessary for modeling the device's failure characteristics. Under this scenario, a device might become obsolete by the time the manufacturer could guarantee its reliability. High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce. This article shows that the use of HVST can dramatically reduce the amount of required burn-in. View full abstract»

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  • Call-for-Papers

    Publication Year: 2006 , Page(s): 99
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  • Changing test and data modeling requirements for screening latent defects as statistical outliers

    Publication Year: 2006 , Page(s): 100 - 109
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB) |  | HTML iconHTML  

    The expanded role of test demands a significant change in mind-set of nearly every engineer involved in the screening of semiconductor products. The issues to consider range from DFT and ATE requirements, to the design and optimization of test patterns, to the physical and statistical relationships of different tests, and finally, to the economics of reducing test time and cost. The identification of outliers to isolate latent defects will likely increase the role of statistical testing in present and future technologies. An emerging opportunity is to use statistical analysis of parametric measurements at multiple test corners to improve the effectiveness and efficiency of testing and reliability defect stressing. In this article, we propose a "statistical testing" framework that combines testing, analysis, and optimization to identify latent-defect signatures. We discuss the required characteristics of statistical testing to isolate the embedded-outlier population; test conditions and test application support for the statistical-testing framework; and the data modeling for identifying the outliers. View full abstract»

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  • Combining negative binomial and Weibull distributions for yield and reliability prediction

    Publication Year: 2006 , Page(s): 110 - 116
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB) |  | HTML iconHTML  

    A key productivity metric in semiconductor manufacturing is wafer test yield - the fraction of dies deemed functional following wafer probe testing. Wafer test yield is directly related to semiconductor manufacturing profitability: The higher the yield, the lower the cost of producing a functional chip, and therefore the greater the potential profit. Because wafer test yield is such a critical variable in a products profit potential, accurate yield projection models are essential to semiconductor manufacturers economic success. It is important to understand the correlation between defects causing yield loss and defects causing reliability failures. This article presents a modeling methodology and supporting data, demonstrating that yield and reliability defects can be directly linked in a unified model. View full abstract»

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  • Call for Papers

    Publication Year: 2006 , Page(s): 117
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  • The impact of multiple failure modes on estimating product field reliability

    Publication Year: 2006 , Page(s): 118 - 126
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    A difficulty in reliability modeling is how to capture the impact of all of the various reliability defect types. The general approach to optimizing burn-in that we describe in this article addresses a multiple-defect environment. The approach has four main parts: (i) modeling the product's failure rate distribution, (ii) establishing the Pareto distribution of reliability defects, (iii) assessing the kinetic information of each reliability defect, and (iv) estimating the DPPM under product use conditions. This article compares and contrasts the acceleration effects of various extrinsic defects found in 130- and 90-nm CMOS technology products. View full abstract»

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  • Call for Papers

    Publication Year: 2006 , Page(s): 127
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  • Test consideration for nanometer-scale CMOS circuits

    Publication Year: 2006 , Page(s): 128 - 136
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB) |  | HTML iconHTML  

    The exponential increase in leakage, the device parameter variations, and the aggressive power management techniques will severely impact IC testing methods. Test technology faces new challenges as faults with increasingly complex behavior become predominant. Design approaches aimed at fixing some of the undesirable effects of nanometric technologies could jeopardize current test approaches. In this article, we explore test considerations for scaled CMOS circuits in the nanometer regime and describe possible solutions to many of these challenges, including statistical timing and delay test, IDDQ test under exponentially increasing leakage, and power or thermal management architectures. View full abstract»

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  • Call for Papers

    Publication Year: 2006 , Page(s): 137
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  • Optical contactless probing: an all-silicon, fully optical approach

    Publication Year: 2006 , Page(s): 138 - 146
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    With decreasing feature size and increasing chip densities, the classical mechanical probe approach for internal fault detection and functional testing faces increasing challenges. Contactless testing might resolve many of the challenges associated with conventional mechanical wafer testing. This article reviews and explains existing optical contactless technologies and introduces a new test methodology - a fully optical contactless testing technique. The proposed method's uniqueness lies in the fact that it is a fully optical technique that uses visible light and is completely compatible with standard silicon IC processing. The technique produces results that demonstrate its feasibility and show its advantages over other optical contactless testing methods. View full abstract»

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  • IEEE Computer Society Information

    Publication Year: 2006 , Page(s): 147
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  • A SystemC refinement methodology for embedded software

    Publication Year: 2006 , Page(s): 148 - 158
    Cited by:  Papers (8)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    This article presents a design environment that provides an interface for user-written SystemC modules that model application software to make calls to a real-time operating system (RTOS) kernel and cosimulate with user-written SystemC hardware modules. The environment also facilitates successive refinement through three abstraction layers for hardware-software codesign suitable for embedded-system design. View full abstract»

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  • Call for Papers

    Publication Year: 2006 , Page(s): 159
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  • Was it worth the wait? Yes!

    Publication Year: 2006 , Page(s): 160 - 161
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  • An insider's look at microprocessor design

    Publication Year: 2006 , Page(s): 162 - 163
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  • ITC 2005 panels

    Publication Year: 2006 , Page(s): 164 - 166
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  • TTTC technical forum honoring Sudhakar M. Reddy

    Publication Year: 2006 , Page(s): 167
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  • CEDA Currents

    Publication Year: 2006 , Page(s): 168 - 171
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty