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Electron Devices, IEEE Transactions on

Issue 4 • Date April 2006

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Displaying Results 1 - 25 of 58
  • Table of contents

    Publication Year: 2006 , Page(s): c1 - 586
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  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2006 , Page(s): c2
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  • Changes to the Editorial Board

    Publication Year: 2006 , Page(s): 587
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  • Device scaling physics and channel velocities in AIGaN/GaN HFETs: velocities and effective gate length

    Publication Year: 2006 , Page(s): 588 - 593
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    This paper addresses scaling issues in AIGaN/GaN heterojunction field-effect transistors (HFETs) using ensemble Monte Carlo techniques. For gate lengths below 0.25 μm, fT values are known not to scale linearly with the inverse gate length. The authors' simulations show this to be due to an increasing difference between the lithographic gate length and the effective gate length as the devices shrink. The results for AIGaN/GaN are compared with In0.52Al0.48-In0.53Ga0.47As-InP devices, and the authors found that the limiting role of velocity overshoot and depletion region spread causes the GaN HFETs to have a peak fT of ∼ 220 GHz compared to ∼ 500 GHz for InGaAs devices. View full abstract»

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  • Inkjetted crystalline single monolayer oligothiophene OTFTs

    Publication Year: 2006 , Page(s): 594 - 600
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    Crystalline monolayer films of a novel organic semiconducting material were deposited as the active layer for organic thin-film transistors (OTFTs) via inkjet printing. Devices exhibited field-effect mobilities up to 0.07 cm2/V·s and on/off ratios >108, surpassing values measured for devices cast with thicker films of the same material. The printed monolayer devices exhibited superior subthreshold characteristics with less hysteresis, and defect and trap densities are improved over thicker film analogs. These results show that solution deposition techniques such as inkjet printing can result in the monolayer crystalline thin films that are requisite for near-ideal electrostatics in OTFTs. View full abstract»

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  • Influence of transistor parameters on the noise margin of organic digital circuits

    Publication Year: 2006 , Page(s): 601 - 610
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    The concept of noise margin is crucial in the design and operation of digital logic circuits. Analytical expressions for the transfer curves of an inverter based on two depletion-mode p-type organic thin-film transistors (OTFTs) were calculated. Based on these expressions, the values for the noise margin of organic-based inverters were calculated. In this paper, the influence of the OTFT parameters on the noise margin is presented. Knowing that statistical variations of the transistor parameters are inherent to OTFT technology, these statistical variations are also taken into account. Finally, a circuit yield analysis is presented. View full abstract»

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  • A 2.0-μm pixel pitch MOS image sensor with 1.5 transistor/pixel and an amorphous Si color filter

    Publication Year: 2006 , Page(s): 611 - 617
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    In this paper, an ultrafine pixel size (2.0×2.0 μm2) MOS image sensor with very high sensitivity is developed. The key technologies that realize the MOS image sensor are a newly developed pixel circuit configuration (1.5 transistor/pixel), a fine 0.15-μm design rule, and an amorphous Si color filter (Si-CF). In the new pixel circuit configuration, a unit pixel consists of one photodiode, one transfer transistor, and an amplifier circuit with two transistors that are shared by four neighboring pixels. Thus, the unit pixel has only 1.5 transistors. The fine design rule of 0.15 μm enables reduction of wiring area by 40%. As a result, a high aperture ratio of 30% is achieved. A newly developed Si-CF realizes the 1/10 thickness of that of the conventional organic-pigment CF, giving rise to high light-collection efficiency. With these three technologies combined, a high sensitivity of 3400 electrons/lx·s is achieved even with a pixel size of 2.0×2.0 μm2. View full abstract»

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  • Statistics of single-electron signals in electron-multiplying charge-coupled devices

    Publication Year: 2006 , Page(s): 618 - 622
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB) |  | HTML iconHTML  

    Electron-multiplying charge coupled devices promise to revolutionize ultrasensitive optical imaging. The authors present a simple methodology allowing reliable measurement of camera characteristics and statistics of single-electron events, compare the measurements to a simple theoretical model, and report camera performance in a truly photon-counting regime that eliminates the excess noise related to fluctuations of the multiplication gain. View full abstract»

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  • CMOS device noise considerations for terabit lightwave systems

    Publication Year: 2006 , Page(s): 623 - 630
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    An improved model to predict sensitivity of p-i-n lightwave receivers using CMOS technology is proposed. This model incorporates the latest understanding of excess channel noise observed in nanoscale MOSFETs. For the case of an ideal channel filter, the results are presented in an analytical closed form. For nonideal channels, the concept of higher order Personick integrals is introduced. Up to 10 Gb/s, the results predicted by the above model closely mimic the existing CMOS data published over the last 20 years. Above 10 Gb/s, due to lack of CMOS data, projections are evaluated against the nonsilicon technologies. The predictions compare very favorably with the measured system performance using high electron mobility transistors and heterojunction bipolar transistors. The findings thus indicate that CMOS should claim its status as the low-cost high-performance highly integrated technology of choice for lightwave applications beyond 10 Gb/s. View full abstract»

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  • Characterization of a CMOS Geiger photodiode pixel

    Publication Year: 2006 , Page(s): 631 - 635
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    This paper examines the performance of CMOS avalanche photodiode pixels operated in a Geiger mode. The pixels, called Geiger photodiode (GPD) pixels, convert an incident analog photon flux into a digital count rate. The maximum detection efficiency of the characterized GPD pixel for 632-nm light is 22%. The passively quenched GPD pixel exhibits an after pulsing at excess bias voltages above 2 V, and a minimum in the after-pulsing correction factor, of 0.53, occurs at an excess bias of 5.8 V. The after pulsing increases the fluctuations, or noise, in the count-rate signal. The following expression accurately describes the noise in the characterized GPD pixel, which exhibits a relatively low after-pulsing probability: σ2=n~dp+n~ap+2·[n~dp·n~ap]12/, where σ represents the count-rate fluctuations, the "dp" subscript stands for "detected photons," the "ap" subscript stands for "after pulses," and the n~ represents the "average count rate of" dp, or ap. The noise-equivalent illumination exhibits a minimum of 300 Hz at an operating voltage of 28 V. The best operating voltage for the GPD pixel increases from 28 V with increasing signal intensity. View full abstract»

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  • Electrical-stress effects and device modeling of 0.18-μm RF MOSFETs

    Publication Year: 2006 , Page(s): 636 - 642
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    In this paper, a novel microstrip-line layout is used to make accurate measurements of the minimum noise figure (NFmin) of RF MOSFETs. A low NFmin of 1.05 dB at 10 GHz was directly measured for 16-finger 0.18-μm MOSFETs, without de-embedding. Using an analytical expression for NFmin, we have developed a self-consistent dc current-voltage, S-parameter, and NFmin model, where the simulated results match the measured device characteristics well, both before and after electrical stress. View full abstract»

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  • Restabilizing mechanisms after the onset of thermal instability in bipolar transistors

    Publication Year: 2006 , Page(s): 643 - 653
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    The electrothermal behavior of single- and two-finger bipolar transistors at medium- and high-current operations is studied through theoretical modeling, experimental measurements, and computer simulations. Bias conditions that border thermally stable and unstable operation regimes are described by novel analytical formulations, which for the first time include simultaneously all relevant parameters that weaken the electrothermal feedback at high currents such as ballasting resistors, current dependence of the base-emitter-voltage temperature coefficient, and high-injection effects. Hence, besides giving a correct description of thermal instability mechanisms, the developed formulations also allow the prediction and physical understanding of restabilization phenomena. The models are supported by measurements on silicon-on-glass n-p-n bipolar junction transistors and by simulation results from a novel SPICE-based electrothermal macromodel for bipolar transistors. Furthermore, the models are employed to analyze the influence of the germanium percentage in the base of SiGe heterojunction bipolar transistors on the thermal ruggedness of the device. View full abstract»

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  • Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation

    Publication Year: 2006 , Page(s): 654 - 662
    Cited by:  Papers (43)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    The charge storage and program/erase mechanisms in polysilicon-oxide-nitride-oxide-silicon (SONOS) memory structures with charge-storage layers of different materials are investigated in this paper. In particular, the use of a HfAlO charge-storage layer in a SONOS-type memory structure is proposed. Compared to other high-κ charge-storage layers, HfAlO has the advantage of high-speed program/erase of HfO2 as well as the good charge-retention time of Al2O3, which makes HfAlO a promising candidate for the charge-storage layer in a SONOS-type memory. The use of HfAlO with different HfO2 and Al2O3 compositions as a blocking-oxide layer in SONOS-type structures is also investigated. View full abstract»

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  • Impact of programming mechanisms on the performance and reliability of nonvolatile memory devices based on Si nanocrystals

    Publication Year: 2006 , Page(s): 663 - 667
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    A nonvolatile memory based on silicon nanocrystals (nc-Si) synthesized with very-low-energy Si+ implantation is fabricated, and the memory performance under the programming/erasing of either Fowler-Nordheim (FN)/FN or channel hot electron (CHE)/FN at both room temperature and 85°C is investigated. The CHE programming has a larger memory window, a better endurance, and a longer retention time as compared to FN programming. In addition, the CHE programming yields less stress-induced leakage current than FN programming, suggesting that it produces less damage to the gate oxide and the oxide/Si interface. Detailed discussions on the impact of the programming mechanisms are presented. View full abstract»

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  • A study of hot-hole injection during programming drain disturb in flash memories

    Publication Year: 2006 , Page(s): 668 - 676
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    Program disturbs in NOR-type Flash arrays significantly degrade the tunnel oxide by hot-hole injection (HHI) induced by band-to-band tunneling at the drain overlap. This paper provides a comprehensive experimental and modeling analysis of HHI in Flash memories under program-disturb conditions. Carrier-separation measurements on arrays of Flash memories with contacted floating-gate (FG) allows for a direct investigation of hole-initiated impact ionization and HHI. A Monte Carlo (MC) model is used to simulate carrier multiplication and injection into the FG. After validating the MC model against experimental data for both secondary electron generation and HHI, the model is used to provide further insight into the hole-injection mechanism. View full abstract»

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  • Quantum-mechanical suppression and enhancement of SCEs in ultrathin SOI MOSFETs

    Publication Year: 2006 , Page(s): 677 - 684
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB) |  | HTML iconHTML  

    This paper simulates the transport characteristics of ultrathin silicon-on-insulator MOSFETs, and evaluates the influence of the quantum-mechanical mechanism on the short-channel effects on the basis of the density-gradient model. It is clearly shown that the quantum-mechanical mechanism suppresses the buried-insulator-induced barrier lowering with regard to the subthreshold swing because the surface dark space yields a high-field region in the source region adjacent to the channel. It is also suggested that the quantum-mechanical mechanism enhances the impact of the apparent charge-sharing effect on the threshold voltage because the surface dark space effectively increases the thickness of the gate-oxide layer and buried-oxide layer. View full abstract»

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  • Analysis of subthreshold carrier transport for ultimate DGMOSFET

    Publication Year: 2006 , Page(s): 685 - 691
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    A novel transport model for the subthreshold mode of double-gate MOSFETs (DGMOSFETs) is proposed in this paper. The model enables the analysis of short-channel effects (SCEs) such as the subthreshold swing (SS), the threshold-voltage rolloff, and the drain-induced barrier lowering. The proposed model includes the effects of thermionic emission and the quantum tunneling of carriers through the source-drain barrier. An approximative solution of the two-dimensional Poisson equation is used for the distribution of the electric potential, and the Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The model is verified by comparing the SS with numerical simulations. The new model is used to investigate the subthreshold characteristics of a DGMOSFET having the gate length in the nanometer range with an ultrathin gate oxide and channel thickness. The SCEs degrade the subthreshold characteristics of DGMOSFETs when the gate length is reduced below 10 nm, and any design in the sub-10-nm-regime should include the effects of quantum tunneling. View full abstract»

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  • A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory

    Publication Year: 2006 , Page(s): 692 - 697
    Cited by:  Papers (37)  |  Patents (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    A capacitorless one-transistor (1T)-dynamic random-access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact-ionization (II) current, the write operation with GIDL current achieves power consumption that is lower by four orders of magnitude and a write speed within several nanoseconds. The capacitorless 1T DRAM is the most promising technology for high-performance embedded-DRAM large-scale integration. View full abstract»

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  • Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection

    Publication Year: 2006 , Page(s): 698 - 705
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    The lateral profile of trapped charge in a silicon-oxide-nitride-oxide-silicon (SONOS) electrically erasable programmable read-only memory programmed using channel-hot-electron injection is determined using current-voltage (ID-VG) measurements along with two-dimensional device simulations and is verified using gate-induced-drain-leakage measurements, charge-pumping (CP) measurements, and Monte Carlo simulations. An iterative procedure is used to match simulated ID-VG characteristics with experimental ID-VG characteristics at different stages of programming, by sequentially increasing the trapped electron charge in simulations. Fresh cells are found to contain a high laterally nonuniform trapped charge, which (along with large electron injection during the program) make the conventional CP techniques inadequate for extracting the charge profile. This charge results in a nonmonotonous variation of threshold and flat-band voltages along the channel and makes it impossible to simultaneously determine interface and trapped charge profiles using CP alone. The CP technique is modified for application to SONOS cells and is used to verify the charge profile obtained using ID-VG and to estimate the interface degradation. This paper enhances the study presented in our earlier work. View full abstract»

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  • Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

    Publication Year: 2006 , Page(s): 706 - 711
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB) |  | HTML iconHTML  

    A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations. View full abstract»

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  • Experimental study of the process dependence of Mo, Cr, Ti, and W silicon Schottky diodes and contact resistance

    Publication Year: 2006 , Page(s): 712 - 718
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB) |  | HTML iconHTML  

    This paper reports on the process dependence and electrical characterization of Schottky diodes and ohmic contacts fabricated on p- and n-type silicon wafers. Four metals are systematically studied using identical test structures and characterization methods: Mo, Ti, W, and Cr. The choice of these metals is motivated by their midgap barriers and compatibility with an integrated circuit technology. For these, a thorough investigation of the variation in Schottky-barrier height and contact resistance is carried out for the following process parameters: 1) predeposition wafer preparation, 2) deposition method (sputtering and e-beam evaporation), 3) deposition temperature for the sputtered samples, and 4) annealing. It is found that RF etching previous to metal deposition increases the contact resistance and the barrier height for diodes on p-type silicon. This is of great importance, since RF etching is a very common in situ cleaning process in microelectronic and microelectromechanical systems technologies. Annealing can be used to restore the values of barrier height and contact resistance on wafers exposed to the RF etching. View full abstract»

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  • Suppression of high-resistance phases of Ni silicide by Se passivation of Si(100)

    Publication Year: 2006 , Page(s): 719 - 723
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    High-resistance phases of Ni-rich Ni silicide are formed on Si(100) below 400°C, while high-resistance phases of Si-rich Ni silicide are formed above 600°C. The desired low-resistance NiSi is formed between 400°C and 600°C. In this paper, the authors report the suppression of high-resistance phases of Ni silicide by passivating the Si(100) surface with a monolayer of Se. A 500-Å Ni on n-type low 1015 cm-3 doped Si(100) wafers, passivated with Se, shows a sheet resistance of ∼2.55 Ω/square upon annealing between 200°C and 500°C, while the sheet resistance of the 500-Å Ni on identical wafers without Se-passivation jumps to ∼7.92 Ω/square between 300°C and 350°C. Between 600°C and 700°C, the sheet resistance of the Se-passivated samples is ∼ 10% lower than that of the control samples. Transmission electron microscopy, X-ray diffraction, and X-ray photoelectron spectroscopy all confirm that the suppression of high-resistance Ni silicides below 500°C is attributed to the suppression of silicidation and above 600°C to the delay in Si-rich Ni silicide formation at the Ni/Se-passivated Si(100) interface. View full abstract»

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  • Performance enhancement of ring oscillators and transimpedance amplifiers by package strain

    Publication Year: 2006 , Page(s): 724 - 729
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    The appropriate external stress can enhance a device and circuit performance. The 7.4% speed enhancement is achieved for the 250-nm node ring oscillator under uniaxial tensile strain for a mutually perpendicular layout of the NFET and the PFET. The speed enhancement is less than 1.5% for the conventional parallel layout of the NFET and the PFET. A 180-nm node transimpedance amplifier has a ∼ 5% bandwidth enhancement using a biaxial tensile strain or a uniaxial tensile strain parallel to the NFET channel to tune the peaking frequency of active inductor in the circuit. The package strain can provide an extra useful parameter for the future digital and analog circuit design. View full abstract»

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  • Influence of Si nanocrystal distributed in the gate oxide on the MOS capacitance

    Publication Year: 2006 , Page(s): 730 - 736
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    In this paper, the authors have studied the influence of silicon nanocrystal (nc-Si) distributed in the gate oxide on the capacitance for the circumstances that the nc-Si does not form conductive percolation tunneling paths connecting the gate to the substrate. The nc-Si is synthesized by Si-ion implantation. The effective dielectric constant of the gate oxide in the nc-Si distributed region is calculated based on a sublayer model of the nc-Si distribution and the Maxwell-Garnett effective medium approximation. After the depth distribution of the effective dielectric constant is obtained, the MOS capacitance is determined. Two different nc-Si distributions, i.e., partial and full nc-Si distributions in the gate oxide, have been considered. The MOS capacitance obtained from the modeling has been compared to the capacitance measurement for a number of samples with various gate-oxide thicknesses, implantation energies and dosages, and an excellent agreement has been achieved for all the samples. A detailed picture of the influence of implantation energy and implantation dosage on the MOS capacitance has been obtained. View full abstract»

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  • Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson's equation

    Publication Year: 2006 , Page(s): 737 - 742
    Cited by:  Papers (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    The potential variation in the channel obtained from analytical solution of three-dimensional (3-D) Poisson's equation is used to calculate the subthreshold current and threshold voltage of fin field-effect transistors with doped and undoped channels. The accuracy of the model has been verified by the data from 3-D numerical device simulator. The variation of subthreshold slope and threshold voltage with device geometry and doping concentration in the channel has been studied. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego