IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • April 2006

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Displaying Results 1 - 17 of 17
  • Table of contents

    Publication Year: 2006, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2006, Page(s): c2
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  • Guest Editorial

    Publication Year: 2006, Page(s):609 - 610
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  • Semi-individual wire-length prediction with application to logic synthesis

    Publication Year: 2006, Page(s):611 - 624
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB) | HTML iconHTML

    A new concept for wire-length prediction, the semi-individual wire-length prediction, is introduced. Structural metrics, such as mutual contraction and net range, are used to predict which interconnects have a tendency to be long or short in the final layout. The very good correlation of the prelayout measures with the postlayout interconnect lengths is demonstrated. The prelayout wire-length-pred... View full abstract»

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  • Technology mapping algorithm targeting routing congestion under delay constraints

    Publication Year: 2006, Page(s):625 - 636
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Routing congestion has become a serious concern in today's very-large-scale-integration designs. To address this, the authors propose a technology mapping algorithm that minimizes routing congestion under delay constraints in this paper. The algorithm employs a dynamic-programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps a... View full abstract»

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  • Modern floorplanning based on B*-tree and fast simulated annealing

    Publication Year: 2006, Page(s):637 - 650
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (856 KB) | HTML iconHTML

    Unlike classical floorplanning that usually handles only block packing to minimize silicon area, modern very large scale integration (VLSI) floorplanning typically needs to pack blocks within a fixed die (outline), and additionally considers the packing with block positions and interconnect constraints. Floorplanning with bus planning is one of the most challenging modern floorplanning problems be... View full abstract»

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  • Delay insertion method in clock skew scheduling

    Publication Year: 2006, Page(s):651 - 663
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB) | HTML iconHTML

    This paper describes a delay insertion method that improves the efficiency of clock skew scheduling. It is shown that reconvergent paths limit the improvement of circuit performance achievable through clock skew scheduling. A delay insertion method is proposed such that the optimal clock period achievable through clock skew scheduling is improved by mitigating the limitations caused by reconvergen... View full abstract»

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  • Partition-based algorithm for power grid design using locality

    Publication Year: 2006, Page(s):664 - 677
    Cited by:  Papers (15)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB) | HTML iconHTML

    This paper presents an efficient heuristic algorithm, which employs successive partitioning and grid-refinement scheme, for designing the power distribution network of a chip. In an iterative procedure, the chip area is recursively bipartitioned, and the wire pitches and the wire widths of the power grid in the partitions are repeatedly adjusted to meet the voltage drop and current-density specifi... View full abstract»

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  • A fast hierarchical quadratic placement algorithm

    Publication Year: 2006, Page(s):678 - 691
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB) | HTML iconHTML

    Placement is a critical component of today's physical-synthesis flow with tremendous impact on the final performance of very large scale integration (VLSI) designs. Unfortunately, it accounts for a significant portion of the overall physical-synthesis runtime. With the complexity and the netlist size of today's VLSI design growing rapidly, clustering for placement can provide an attractive solutio... View full abstract»

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  • Placement of thermal vias in 3-D ICs using various thermal objectives

    Publication Year: 2006, Page(s):692 - 709
    Cited by:  Papers (80)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB) | HTML iconHTML

    As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the effective-thermal resistance of the chip. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while plac... View full abstract»

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  • Fast interval-valued statistical modeling of interconnect and effective capacitance

    Publication Year: 2006, Page(s):710 - 724
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB) | HTML iconHTML

    Correlated interval representations of range uncertainty offer an attractive solution to approximating computations on statistical quantities. The key idea is to use finite intervals to approximate the essential mass of a probability density function (pdf) as it moves through numerical operators; the resulting compact interval-valued solution can be easily interpreted as a statistical distribution... View full abstract»

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  • Global routing by iterative improvements for two-layer ball grid array packages

    Publication Year: 2006, Page(s):725 - 733
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    In current very large scale integration (VLSI) circuits, there can be hundreds of required I/O pins. Ball grid array (BGA) packaging is commonly used to realize the huge number of connections between VLSI chips and printed circuit boards (PCBs). In this paper, the authors propose a global-routing method by iterative improvements for two-layer BGA packages. In their routing model, the global routin... View full abstract»

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  • Antenna avoidance in layer assignment

    Publication Year: 2006, Page(s):734 - 738
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    The sustained progress of very-large-scale-integration (VLSI) technology has dramatically increased the likelihood of the antenna problem in the manufacturing process and calls for corresponding considerations in the routing stage. In this paper, the authors propose a technique that can handle the antenna problem during the layer-assignment (LA) stage, which is an important step between global rou... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2006, Page(s): 739
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  • IEEE Biomedical Circuits and Systems Conference healthcare technology (BiOCAS 2006)

    Publication Year: 2006, Page(s): 740
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2006, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2006, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu