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Solid-State Circuits, IEEE Journal of

Issue 4 • Date April 2006

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Displaying Results 1 - 25 of 31
  • [Front cover]

    Page(s): c1 - c4
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    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits publication information

    Page(s): c2
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    Freely Available from IEEE
  • Table of contents

    Page(s): 745 - 746
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    Freely Available from IEEE
  • Introduction to the Special Issue on the 2005 Symposium on VLSI Circuits

    Page(s): 747 - 748
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    Freely Available from IEEE
  • Enhancing microprocessor immunity to power supply noise with clock-data compensation

    Page(s): 749 - 758
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    This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show through extensive analysis techniques that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on 130- and 180-nm processors validate the approach. View full abstract»

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  • A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor

    Page(s): 759 - 771
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    The floating-point unit (FPU) in the synergistic processor element (SPE) of a CELL processor is a fully pipelined 4-way single-instruction multiple-data (SIMD) unit designed to accelerate media and data streaming with 128-bit operands. It supports 32-bit single-precision floating-point and 16-bit integer operands with two different latencies, six-cycle and seven-cycle, with 11 FO4 delay per stage. The FPU optimizes the performance of critical single-precision multiply-add operations. Since exact rounding, exceptions, and de-norm number handling are not important to multimedia applications, IEEE correctness on the single-precision floating-point numbers is sacrificed for performance and simple design. It employs fine-grained clock gating for power saving. The design has 768K transistors in 1.3 mm2, fabricated SOI in 90-nm technology. Correct operations have been observed up to 5.6 GHz with 1.4 V and 56°C, delivering 44.8 GFlops. Architecture, logic, circuits, and integration are codesigned to meet the performance, power, and area goals. View full abstract»

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  • Pulsed current-mode signaling for nearly speed-of-light intrachip communication

    Page(s): 772 - 780
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    In this paper, we describe the design of on-chip repeater-less interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8-Gb/s serial link employing this pulsed current-mode signaling in a 0.18-μm CMOS process is described and measured. View full abstract»

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  • AES-Based Security Coprocessor IC in 0.18- \mu\hbox {m} CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

    Page(s): 781 - 792
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    Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-$muhbox m$CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions. View full abstract»

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  • A self-tuning DVS processor using delay-error detection and correction

    Page(s): 792 - 804
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    In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which incorporates an in situ error detection and correction mechanism to recover from timing errors. We also present the implementation details and silicon measurements results of a 64-bit processor fabricated in 0.18-μm technology that uses Razor for supply voltage control. Traditional DVS techniques require significant voltage safety margins to guarantee computational correctness at the worst case combination of process, voltage and temperature conditions, leading to a loss in energy efficiency. In Razor-based DVS, however, the supply voltage is automatically reduced to the point of first failure using the error detection and correction mechanism, thereby eliminating safety margins while still ensuring correct operation. In addition, the supply voltage can be intentionally scaled below the point of first failure of the processor to achieve an optimal tradeoff between energy savings from further voltage reduction and energy overhead from increased error detection and correction activity. We tested and measured savings due to Razor DVS for 33 different dies and obtained an average energy savings of 50% over worst case operating conditions by scaling supply voltage to achieve a 0.1% targeted error rate, at a fixed frequency of 120 MHz. View full abstract»

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  • Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

    Page(s): 805 - 814
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    This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage VDD and threshold voltage VTH in active and standby modes. In the active mode, on the basis of delay monitoring results, either VDD control or VTH control is selected to avoid any oscillation problem between them. In VDD control, on the basis of delay monitoring results, VDD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In VTH control, on the basis of power monitoring results, VTH is adjusted so as to maintain a certain switching current ISW/leakage current ILEAK ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current ISUBTH to substrate current ISUB) is improved by taking into consideration both the effects of lowering VDD and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the ISW/ILEAK ratio in the active mode and 2) detect optimum body bias conditions (ISUBTH=ISUB) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode. View full abstract»

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  • A low leakage SRAM macro with replica cell biasing scheme

    Page(s): 815 - 822
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    For mobile applications of SRAMs, there is a need to reduce standby current leakages while keeping memory cell data. For this purpose, we propose a replica cell biasing scheme which controls the cell bias voltage by self-tuning using replica cells. This scheme minimizes the cell leakage regardless of the process fluctuations and the environmental conditions. In addition, leakage reduction in row decoder circuits is also desirable, because standby current leakages in peripheral circuits are dominated by row decoders. We also propose a row decoder circuit which can reduce both the off-leakage and the gate-leakage in the row decoders. We fabricated a 90-nm 512-Kb low-leakage SRAM macro to verify the proposed leakage reduction techniques. With these techniques, 88% reduction of the standby leakage in the sleep mode and 40% reduction of the leakage compared with the conventional diode clamp scheme are realized. View full abstract»

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  • An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology

    Page(s): 823 - 830
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    An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area, and low voltage level of wordline are controlled. A 512-kb test SRAM chip, fabricated with an 80-nm double stacked cell technology, shows that average power consumption is reduced by 9% and the standard deviation decreases by 58%. View full abstract»

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  • A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques

    Page(s): 831 - 838
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    A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and CIO minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented. View full abstract»

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  • A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC

    Page(s): 839 - 850
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    This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage ΔΣ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q2 Random Walk switching scheme. The ΔΣ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage ΔΣ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-μm CMOS technology with active area of 1.11mm2 including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm2. The total power consumption of the DDFS is 200mW with a 3.3-V power supply. View full abstract»

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  • A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

    Page(s): 851 - 858
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    In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640H×480V pixels), 7.5×7.5 μm2 pixel color CMOS image sensor fabricated through 0.35-μm two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity. View full abstract»

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  • Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)

    Page(s): 859 - 867
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    The analog T-switch (AT-switch) scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitors and sample-and-hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-μm FD-SOI process with low VTH of 0.1 V using the concept. The scheme is compared with another leakage-suppression scheme based on super cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on AT-switch greatly improves 8.1-dB SNDR through reducing nonlinear leakage effects while the modulator based on SCCMOS improves the dynamic range rather than the SNDR by comparing with the conventional sigma-delta modulator. View full abstract»

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  • A CMOS oversampled DAC with multi-bit semi-digital filtering and boosted subcarrier SNR for ADSL central office modems

    Page(s): 868 - 875
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    An oversampled digital-to-analog converter for use in ADSL central office modems has been integrated in 0.18-μm CMOS technology. The converter features a multi-bit semi-digital filter for reconstruction and a digital pre-emphasis filter that boosts the SNR of subcarriers affected by noise shaping and flattens the overall in-band magnitude response. A resampled impulse response is employed to simplify the implementation of the semi-digital filter. The combination of digital and semi-digital filtering allows the design to meet all ADSL performance requirements with only 180 current cells and a third-order analog low-pass reconstruction filter. When sampling at 200 MSample/s, the converter achieves 86-dB dynamic range for a 1.1-MHz bandwidth, with an average MTPR of 65 dB. View full abstract»

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  • An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

    Page(s): 876 - 882
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    A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order ΣΔ modulator with 3.8-μVrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 μW, respectively, at a single 0.9-V supply. The core area is 0.5 mm2 in a 0.25-μm standard CMOS technology. View full abstract»

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  • A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

    Page(s): 883 - 890
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    This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment temperature, and power-supply voltage, as well as the variations in chip fabrication. It utilizes information from the digital calibration process and does not require additional analog circuits. The prototype ADC occupies an area of 0.5×2.3 mm2 in a 0.18-μm dual-gate CMOS technology; with a power supply of 2.8 V, it consumes 19.2, 33.7, 50.5, and 72.8 mW when operating at 10, 20, 30, and 40 MS/s, respectively. The peak differential nonlinearity (DNL) is less than 0.5 least significant bit (LSB) for all the sampling speeds with temperature variation up to 80°C. When operated at 20 MS/s with 1-MHz input, the ADC achieves 72.1-dB SNR and 71.1-dB SNDR. View full abstract»

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  • A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and ±2.5-cm range finding

    Page(s): 891 - 898
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    A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in 0.18-μm CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of ±2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mW, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mW. The range for data communication is 1 m with BER of 10-3. For ranging applications, the transmitter can reduce the power to 0.7 μW for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 μV/m, and thus the UWB system can be operated even under the current Japan radio regulations. View full abstract»

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  • A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS

    Page(s): 899 - 908
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    A 20-GHz phase-locked loop with 4.9 pspp/0.65 psrms jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-gm oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-μm CMOS operates from 17.6 to 19.4GHz and dissipates 480mW. View full abstract»

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  • A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s

    Page(s): 909 - 917
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    This paper describes a fully differential 3-tap finite impulse response filter in 90-nm CMOS. A traditional traveling wave filter topology is modified to alleviate its inherent delay-bandwidth-gain tradeoffs. Each tap gain is comprised of two transconductors whose outputs superimpose with the same group delay, similar to a distributed amplifier. This doubles the bandwidth of the filter for a given tap spacing and gain. Digital control is provided for the tap gains, an integrated pre-amplifier, and tuning varactors. Coupled differential spirals are used in the delay lines to help the design fit into an area 600 μm×500 μm. A 1-V supply voltage and 25-mW power consumption are enabled by the use of parallel differential pairs for sign control of the transconductances instead of Gilbert cell amplifiers. The input return loss is better than 16 dB and the output return loss is better than 9 dB up to 30 GHz. Equalization of NRZ data over a coaxial cable channel was demonstrated up to 30 Gb/s, making it faster than any previously reported CMOS equalizer. View full abstract»

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  • Notice of Violation of IEEE Publication Principles
    A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit

    Page(s): 918 - 934
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    Notice of Violation of IEEE Publication Principles

    "A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit"
    by Maxim, A.
    in the IEEE Journal of Solid-State Circuits,
    Volume 41, Issue 4, April 2006 Page(s):918 - 934

    After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.

    Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

    C. Turinici, D. Smith, S. Dupue

    Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

    Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

    Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A multi-rate 9.953-12.5-GHz low phase noise LC oscillator was realized in a 90-GHz f/sub T/ 0.2 μm SiGe BiCMOS process. It achieves a 36% tuning range by combining a 35% open-loop frequency calibration range having a sub-0.1% residual error with a 1% closed-loop varactor frequency tuning. The oscillator gain is below 130 MHz/V, while having less than 10% variation over the entire tuning range. The varactor is realized with multiple parallel-connected cells consisting of constant capacitors and voltage-controlled resistors that bring a lower process variation and a higher quality factor in- comparison with standard diode and MOS varactors. A dual regulator architecture was used to provide both high PSRR and low output voltage noise. The supply pushing was reduced below 100 kHz/V by using a pushing cancellation circuit that balances the negative and positive voltage coefficients of the different nonlinear capacitors connected to the LC tank. A discrete-time automatic amplitude control loop using a variable tail resistor architecture was implemented to optimize the VCO's phase noise performance. The VCO specifications include 9.953-12.5-GHz frequency range, 0.1% frequency calibration error, -122 dBc/Hz phase noise at 1 MHz offset, <3 kHz 1/f/sup 3/ corner frequency, <-80 dBc spurious tones, 250×400 μm/sup 2/ die area and 5-mA bias current from a 3.3-V supply. View full abstract»

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  • A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter

    Page(s): 935 - 944
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    A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-μm CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each pipeline stage; hence the effective feedback delay requirement is relaxed by 6×. Code-overlapping of the 1.5-bit pipeline stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with ±0.25 LSB and ±0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8×1.6 mm2 chip consumes 780 mW of power from a 1.8-V power supply. View full abstract»

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  • A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications

    Page(s): 945 - 953
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    A CMOS RF digitally programmable gain amplifier (RF PGA), covering various terrestrial mobile digital TV standards (DMB, ISDB-T, and DVB-H) is implemented as a part of a low-IF tuner IC using 0.18-μm CMOS technology. An improvement of 13-dB IIP3 is attained without significant degradation of other performance criteria like gain, noise figure, common-mode rejection ratio, etc., at similar power consumption. This is achieved by applying a newly proposed differential circuit gm" (the second derivatives of transconductance) cancellation technique, called the differential multiple gated transistor (DMGTR). In the DMGTR amplifier, the negative value of gm" in the fully differential amplifier can be compensated by the positive value of gm" in the pseudo differential amplifier which is properly sized and biased. By adopting the DMGTR, a low-power highly linear RF PGA is implemented. Also, in order to have wide gain range with fine step resolution, a new RF PGA architecture is proposed. The measurement results of the proposed RF PGA exhibit 50-dB gain range with 0.25-dB resolution, 4.5-dB noise figure, a -4-dBm IIP3 (maximum 30 dBm) and 25-dB gain at 16-mW power consumption. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan