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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 2 • Date Feb. 2006

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2006, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2006, Page(s): c2
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  • An asynchronous architecture for modeling intersegmental neural communication

    Publication Year: 2006, Page(s):97 - 110
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1366 KB) | HTML iconHTML

    This paper presents an asynchronous VLSI architecture for modeling the oscillatory patterns seen in segmented biological systems. The architecture emulates the intersegmental synaptic connectivity observed in these biological systems. The communications network uses address-event representation (AER), a common neuromorphic protocol for data transmission. The asynchronous circuits are synthesized u... View full abstract»

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  • A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm

    Publication Year: 2006, Page(s):111 - 121
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (493 KB) | HTML iconHTML

    Image feature separation is a crucial step for image segmentation in computer vision systems. One efficient and powerful approach is the unsupervised clustering of the resulting data set; however, it is a very computationally intensive task. This paper presents a high-performance architecture for unsupervised data clustering. This architecture is suitable for VLSI implementations. It exploits para... View full abstract»

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  • Energy optimization of pipelined digital systems using circuit sizing and supply scaling

    Publication Year: 2006, Page(s):122 - 134
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (715 KB) | HTML iconHTML

    We present a systematic method for minimizing the energy of pipelined digital systems, through joint optimization of each pipeline stage and the system. A pipeline stage with a constant load can either be optimized for delay at a given input size, minimized for energy at a fixed delay, or have delay traded off for energy at a fixed input size. The results of these optimizations are combined to yie... View full abstract»

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  • Energy management for battery-powered reconfigurable computing platforms

    Publication Year: 2006, Page(s):135 - 147
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (753 KB) | HTML iconHTML

    We define portable reconfigurable computing platforms as those which have some form of configurable logic coupled with other on-chip or off-chip processing units such as soft processors, embedded processors, and voltage-scalable processors. In the first part of this paper, we present and test a unique methodology where we dynamically change the active area of a field programmable gate array (FPGA)... View full abstract»

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  • Low-power network-on-chip for high-performance SoC design

    Publication Year: 2006, Page(s):148 - 160
    Cited by:  Papers (73)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1830 KB) | HTML iconHTML

    An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-on-chip (SoC) design. It incorporates heterogeneous intellectual properties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IPs, which op... View full abstract»

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  • Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints

    Publication Year: 2006, Page(s):161 - 172
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (694 KB) | HTML iconHTML

    Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints de... View full abstract»

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  • A combined gate replacement and input vector control approach for leakage current reduction

    Publication Year: 2006, Page(s):173 - 182
    Cited by:  Papers (28)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (581 KB) | HTML iconHTML

    Input vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on lea... View full abstract»

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  • A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

    Publication Year: 2006, Page(s):183 - 192
    Cited by:  Papers (5)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (730 KB) | HTML iconHTML

    Double-gate (DG) transistor has emerged as one of the most promising devices for nano-scale circuit design. In this paper, we propose a high-performance and robust sense-amplifier design using independent gate control in symmetric and asymmetric DG devices for sub-50-nm technologies. The proposed sense amplifier has better performance (30%-35% less sensing delay) and robustness (60%-80% less minim... View full abstract»

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  • X-masking during logic BIST and its impact on defect coverage

    Publication Year: 2006, Page(s):193 - 202
    Cited by:  Papers (17)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (859 KB) | HTML iconHTML

    We present a technique for making a circuit ready for logic built-in self test by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabil... View full abstract»

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  • Layout-driven architecture synthesis for high-speed digital filters

    Publication Year: 2006, Page(s):203 - 207
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    We propose a floorplan-aware complexity reduction methodology for digital filters. Conventional methodologies for complexity reduction use logic-centric approaches focusing on the total number of adders. Therefore, there is a need to consider interconnects to reduce communication costs while synthesizing reduced-complexity filters. In this paper, we integrate high-level synthesis and floorplan to ... View full abstract»

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  • A low-power correlation-derivative CMOS VLSI circuit for bearing estimation

    Publication Year: 2006, Page(s):207 - 212
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (617 KB) | HTML iconHTML

    We present a CMOS integrated circuit (IC) for bearing estimation in the low-audio range that performs a correlation derivative approach in a 0.35-/spl mu/m technology. The IC calculates the bearing angle of a sound source with a mean variance of one degree in a 360/spl deg/ range using four microphones: one pair is used to produce the indication and the other to define the quadrant. An adaptive al... View full abstract»

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  • Comments on "Carry checking/parity prediction adders and ALUs"

    Publication Year: 2006, Page(s):212 - 213
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (105 KB) | HTML iconHTML

    In this brief, it is shown that the checking or comparison of normal carries versus duplicated carries in a carry checking/parity prediction adder can be partially avoided, making it feasible to implement a less complex checker when using a robust logic style. View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2006, Page(s): 214
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  • IEEE order form for reprints

    Publication Year: 2006, Page(s): 215
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2006, Page(s): 216
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2006, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2006, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu