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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 1 • Date Jan. 2006

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Displaying Results 1 - 16 of 16
  • Table of contents

    Publication Year: 2006, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2006, Page(s): c2
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  • Designing via-configurable logic blocks for regular fabric

    Publication Year: 2006, Page(s):1 - 14
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (982 KB) | HTML iconHTML

    In this paper, we describe the design process of a via-configurable logic block for regular fabric. The block consists of a via-configurable functional cell and two via-configurable inverter arrays. A via-configurable functional cell can efficiently implement most commonly used CMOS static cells, and a via-configurable inverter array is efficient in implementing inverters, repeaters, and some pass... View full abstract»

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  • A DPS array with programmable resolution and reconfigurable conversion time

    Publication Year: 2006, Page(s):15 - 22
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2192 KB) | HTML iconHTML

    A CMOS digital pixel sensor (DPS) with programmable resolution and reconfigurable conversion time is described. The chip features a unique architecture based on the pulse width modulation (PWM) technique and operates with either an 8-b or 4-b accuracy. The 8-b conversion mode is used for high-precision imaging while the 4-b conversion mode provides a shorter conversion time and a two times increas... View full abstract»

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  • SWAN: high-level simulation methodology for digital substrate noise generation

    Publication Year: 2006, Page(s):23 - 33
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1024 KB) | HTML iconHTML

    Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This pa... View full abstract»

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  • Efficient built-in redundancy analysis for embedded memories with 2-D redundancy

    Publication Year: 2006, Page(s):34 - 42
    Cited by:  Papers (46)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (867 KB) | HTML iconHTML

    A novel redundant mechanism is proposed for embedded memories in this paper. Redundant rows and columns are added into the memory array as in the conventional approaches. However, the redundant rows and columns are divided into row blocks and column blocks, respectively. The reconfiguration is performed at the row (column) block level instead of the conventional row (column) level. Based on the pr... View full abstract»

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  • An area-efficient universal cryptography processor for smart cards

    Publication Year: 2006, Page(s):43 - 56
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (967 KB) | HTML iconHTML

    Cryptography circuits for smart cards and portable electronic devices provide user authentication and secure data communication. These circuits should, in general, occupy small chip area, consume low power, handle several cryptography algorithms, and provide acceptable performance. This paper presents, for the first time, a hardware implementation of three standard cryptography algorithms on a uni... View full abstract»

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  • Design and verification of SystemC transaction-level models

    Publication Year: 2006, Page(s):57 - 68
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (519 KB) | HTML iconHTML

    Transaction-level modeling allows exploring several SoC design architectures, leading to better performance and easier verification of the final product. In this paper, we present an approach to design and verify SystemC models at the transaction level. We integrate the verification as part of the design flow where we first model both the design and the properties (written in Property Specificatio... View full abstract»

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  • Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction

    Publication Year: 2006, Page(s):69 - 80
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (745 KB) | HTML iconHTML

    According to the International Technology Roadmap for Semiconductors (ITRS), the minimum feature size for microprocessors will shrink to 40 nm by 2010. Leakage currents in devices fabricated at these dimensions have been shown to be so dominant that design methodologies driven by power budgets will face challenges in reducing static power in addition to active power. An effective solution to tackl... View full abstract»

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  • A power-driven multiplication instruction-set design method for ASIPs

    Publication Year: 2006, Page(s):81 - 85
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (323 KB) | HTML iconHTML

    This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to ... View full abstract»

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  • Study of energy and performance of space-time decoding systems in concatenation with turbo decoding

    Publication Year: 2006, Page(s):86 - 90
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB) | HTML iconHTML

    Recent studies have shown that using space-time code is an effective approach to increase the data rate over wireless channels. Space-time turbo (ST-Turbo) codes formed by concatenating space-time codes with turbo codes, take advantage of both the high diversity order of space-time systems and the randomness of the turbo codes. In this paper, we compare two ST-Turbo codes, i.e., simple space-time ... View full abstract»

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  • Estimation of fault-free leakage current using wafer-level spatial information

    Publication Year: 2006, Page(s):91 - 94
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (343 KB) | HTML iconHTML

    Leakage current or the I/sub DDQ/ test has been shown to be an effective test screen in combination with traditional test methods. However, leakage current is rising rapidly as semiconductor technology advances. This makes it difficult to distinguish between faulty and fault-free chips using traditional threshold setting methods. This paper presents a method to estimate leakage current using neigh... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2006, Page(s): 95
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  • IEEE order form for reprints

    Publication Year: 2006, Page(s): 96
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2006, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2006, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu