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IEEE Micro

Issue 1 • Date Jan.-Feb. 2006

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Displaying Results 1 - 21 of 21
  • [Front cover]

    Publication Year: 2006, Page(s): c1
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    Freely Available from IEEE
  • Table of contents

    Publication Year: 2006, Page(s):2 - 3
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  • Masthead

    Publication Year: 2006, Page(s): 4
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  • Measuring the impact of microarchitectural ideas

    Publication Year: 2006, Page(s):5 - 6
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  • Format wars all over again

    Publication Year: 2006, Page(s): 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB) | HTML iconHTML

    Sometime soon Sony intends to embed Blu-Ray, a new optical disc format, in the PlayStation 3 and Sony’s VCRs. Sony has gone to great lengths to generate a coalition of firms to support Blu-Ray. Opposing it is the high-definition DVD, sponsored and supported by many firms, including Toshiba, NEC, Sanyo, Microsoft, and Intel. View full abstract»

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  • Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences

    Publication Year: 2006, Page(s):8 - 9
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  • Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance

    Publication Year: 2006, Page(s):10 - 20
    Cited by:  Papers (12)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (163 KB) | HTML iconHTML

    Today's high-performance processors face main-memory latencies on the order of hundreds of processor clock cycles. As a result, even the most aggressive processors spend a significant portion of their execution time stalling and waiting for main-memory accesses to return data to the execution core. Runahead execution is a promising way to tolerate long main-memory latencies because it has modest h... View full abstract»

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  • Adaptive History-Based Memory Schedulers for Modern Processors

    Publication Year: 2006, Page(s):22 - 29
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (178 KB) | HTML iconHTML

    Careful memory scheduling can increase memory bandwidth and overall system performance. We present a new memory scheduler that makes decisions based on the history of recently scheduled operations, providing two advantages: it can better reason about the delays associated with complex DRAM structure, and it can adapt to different observed workload View full abstract»

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  • Scalable Load and Store Processing in Latency-Tolerant Processors

    Publication Year: 2006, Page(s):30 - 39
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (149 KB) | HTML iconHTML

    Memory latency tolerant architectures achieve high performance by supporting thousands of in-flight instructions without scaling cycle-critical processor resources. We present new load-store processing algorithms for latency tolerant architectures. We augment primary load and store queues with secondary buffers. The secondary load buffer is a set associative structure, similar to a cache. The seco... View full abstract»

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  • Tolerating Cache-Miss Latency with Multipass Pipelines

    Publication Year: 2006, Page(s):40 - 47
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (114 KB) | HTML iconHTML

    Microprocessors exploit instruction-level parallelism and tolerate memory-access latencies to achieve high-performance. Out-of-order microprocessors do this by dynamically scheduling instruction execution, but require power-hungry hardware structures. This article describes multipass pipelining, a microarchitectural model that provides an alternative to out-of-order execution for tolerating memory... View full abstract»

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  • Wish Branches: Enabling Adaptive and Aggressive Predicated Execution

    Publication Year: 2006, Page(s):48 - 58
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (155 KB) | HTML iconHTML

    We propose a mechanism in which the compiler generates code that can be executed either as predicated code or nonpredicated code. The compiler-generated code is the same as predicated code, except the predicated conditional branches are not removed - they are left intact in the program code. These conditional branches are called wish branches. The goal of wish branches is to use predicated executi... View full abstract»

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  • Unbounded Transactional Memory

    Publication Year: 2006, Page(s):59 - 69
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (167 KB) | HTML iconHTML

    This article advances the following thesis: transactional memory should be virtualized to support transactions of arbitrary footprint and duration. Such support should be provided through hardware and be made visible to software through the machines instruction set architecture. We call a transactional memory system unbounded if the system can handle transactions of arbitrary duration that have fo... View full abstract»

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  • Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays

    Publication Year: 2006, Page(s):70 - 79
    Cited by:  Papers (13)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    Cache-coherent shared-memory multiprocessors have wide-ranging applications, from commercial transaction processing and database services to large-scale scientific computing. Coarse-grain coherence tracking (CGCT) is a new technique that extends a conventional coherence mechanism and optimizes coherence enforcement. It monitors the coherence status of large regions of memory and uses that informat... View full abstract»

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  • Energy-Efficient Thread-Level Speculation

    Publication Year: 2006, Page(s):80 - 91
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (270 KB) | HTML iconHTML

    Chip multiprocessors with thread-level speculation have become the subject of intense research, this article refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism View full abstract»

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  • Opportunistic Transient-Fault Detection

    Publication Year: 2006, Page(s):92 - 99
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (114 KB) | HTML iconHTML

    CMOS scaling continues to enable faster transistors and lower supply voltage, improving microprocessor performance and reducing per-transistor power. The downside of scaling is increased susceptibility to soft errors due to strikes by cosmic particles and radiation from packaging materials. The result is degraded reliability in future commodity microprocessors. The authors target better coverage w... View full abstract»

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  • BugNet: Recording Application-Level Execution for Deterministic Replay Debugging

    Publication Year: 2006, Page(s):100 - 109
    Cited by:  Papers (5)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (161 KB) | HTML iconHTML

    With software's increasing complexity, providing efficient hardware support for software debugging is critical. Hardware support is necessary to observe and capture, with little or no overhead, the exact execution of a program. Providing this ability to developers will allow them to deterministically replay and debug an application to pin-point the root cause of a bug View full abstract»

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  • Architectures for Bit-Split String Scanning in Intrusion Detection

    Publication Year: 2006, Page(s):110 - 117
    Cited by:  Papers (20)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (115 KB) | HTML iconHTML

    String matching is a critical element of modern intrusion detection systems because it lets a system make decisions based not just on headers, but actual content flowing through the network. Through careful codesign and optimization of an architecture with a new string matching algorithm, the authors show it is possible to build a system that is almost 12 times more efficient than the currently be... View full abstract»

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  • Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance

    Publication Year: 2006, Page(s):119 - 129
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (342 KB) | HTML iconHTML

    A general dynamic-compilation environment offers power and performance control opportunities for microprocessors. The authors propose a dynamic-compiler-driven runtime voltage and frequency optimizer. A prototype of their design, implemented and deployed in a real system, achieves energy savings of up to 70 percent View full abstract»

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  • Temperature-Aware On-Chip Networks

    Publication Year: 2006, Page(s):130 - 139
    Cited by:  Papers (12)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB) | HTML iconHTML

    On-chip networks are becoming increasingly popular as a way to connect high-performance single-chip computer systems, but thermal issues greatly limit network design. Sirius, an thermal modeling and simulation framework combines with ThermalHerd, a distributed runtime scheme for thermal management to offer a path to thermally efficient on-chip network design View full abstract»

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  • The future will soon be here

    Publication Year: 2006, Page(s):141 - 142
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    Freely Available from IEEE
  • How to write a patent

    Publication Year: 2006, Page(s): 144
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (78 KB) | HTML iconHTML

    In my last column, I showed how to write patent claims in a very broad manner. This time, I’ll talk about writing the rest of the patent. View full abstract»

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Aims & Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center