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Computers and Digital Techniques, IEE Proceedings -

Issue 1 • Date 10 Jan. 2006

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Displaying Results 1 - 7 of 7
  • Memory test experiment: industrial results and data

    Publication Year: 2006 , Page(s): 1 - 8
    Cited by:  Papers (10)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (130 KB)  

    The results of 12 well-known and three fault-primitive-based memory test algorithms applied to 0.13 micron technology 512 kB single-port SRAMs are presented. Each test algorithm is used with up to 16 different stress combinations (SCs) (i.e. different address sequences, data backgrounds and voltages) resulting in 122 tests. The results show that SCs influence the fault coverage (FC) of the test algorithms, that the highest FC is obtained at a low voltage level and that the highest detected number of unique faults is obtained at a high voltage level. They also show that the tests with the most promising FC, based on the theory, also tend to have the highest FC in practice. Moreover, the test results show that some algorithms detect faults that cannot be explained with the existing fault models, indicating that the existing fault models still leave much to be explained; for example, no theoretical basis exists to model the stresses and the predicted FC for a given test. View full abstract»

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  • Theory and practice of automatic design constraint generation

    Publication Year: 2006 , Page(s): 9 - 19
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (233 KB)  

    Design verification and test generation require the modelling of an environment for circuit under consideration. The task is complex, time consuming and error prone. In dynamic circuits, the presence of multiple clocks makes the problem even worse because of the multiplicity of clocking configurations under which the circuit can be instantiated. A technique is presented, which when provided with a set of user-specified inputs regarding environmental assumptions, can automatically generate all design constraints that can be used as environmental models for verification/test obligations. Experiments on real-life industrial strength circuits show that the technique is effective. View full abstract»

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  • Design and implementation of a Java processor

    Publication Year: 2006 , Page(s): 20 - 30
    Cited by:  Papers (9)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (175 KB)  

    Java is widely applied in current embedded systems due to its object-oriented features and advantages such as security, robustness, and platform independence. A Java virtual machine is needed to execute Java programs. However, in most of the existing solutions to Java virtual machines, the overhead of executing object-oriented related instructions is significant and becomes the bottleneck of system performance. To solve this problem, a novel Java processor called jHISC is proposed, which mainly targets J2ME and embedded applications. In jHISC, the object-oriented related instructions are implemented by hardware directly, as a hardware-readable data structure is used to represent the object. The complete system with 4 kB instruction cache and 8 kB data cache is described by VHDL and implemented in a Xilinx Virtex FPGA. It occupies 601 859 equivalent gates and the maximum clock frequency of the system is about 30 MHz. Compared with PicoJava II, the overall performance is speeded up 1 to 7.4 times and the execution efficiency of object-oriented related bytecodes is improved by 0.91 to 13.2 times for the same clock frequency. View full abstract»

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  • Linear complexity of modulo-m related prime sequences

    Publication Year: 2006 , Page(s): 31 - 38
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (149 KB)  

    The linear complexity of m-phase related prime sequences is investigated for the case when m is composite. For each relatively prime factor pik of m, the linear complexity and the characteristic polynomial of the shortest linear feedback shift register that generates the pik-phase version of the sequence can be deduced and these results can then be combined using the Chinese remainder theorem to derive the m-phase values. These values are shown to depend on the categories of the sequence length computed modulo each factor of m, rather than on the category of the length modulo m itself, and that these values depend on the primitive roots employed. For a given length, the highest values of linear complexity result from constructing the sequences using those values of primitive elements that lead to non-zero categories for each factor of m. View full abstract»

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  • Reducing the number of specified values per test vector by increasing the test set size

    Publication Year: 2006 , Page(s): 39 - 46
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (131 KB)  

    Test sets consisting of incompletely specified test vectors for full-scan circuits have applications in input test data compression and power reduction. Earlier procedures for reducing the percentage of specified values in a given test set maintained the test set size. A procedure is described that starts from a given (compact) test set and reduces the percentage of specified values by replacing a selected test vector with a subset of test vectors that have fewer specified values per test vector and together detect the same subset of faults. By applying this replacement process iteratively, the procedure provides a series of solutions with increasing test set sizes and decreasing numbers of specified values per test vector. The importance of considering a series of solutions is demonstrated in the application of input test data compression. View full abstract»

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  • Gigabyte per second streaming lossless data compression hardware based on a configurable variable-geometry CAM dictionary

    Publication Year: 2006 , Page(s): 47 - 58
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (285 KB)  

    A high-throughput lossless data compression IP core built around a CAM-based dictionary whose number of available entries and data word width adjust to the characteristics of the incoming data stream is presented. These two features enhance model adaptation to the input data, improving compression efficiency, and enable greater throughputs as a multiplicity of bytes can be processed per cycle. A parsing mechanism adjusts the width of dictionary words to natural words while the length of the dictionary grows from an initial empty state to a maximum value defined as a run-time configuration parameter. The compressor/decompressor architecture was prototyped on an FPGA-based PCI board. An ASIC hard-macro was subsequently implemented and achieved a throughput of more than 1 gigabyte per second when clocking at 277 MHz on a high-performance, 0.13 μm, eight-layer copper CMOS process. View full abstract»

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  • Memory access scheduling and binding considering energy minimisation in multi-bank memory systems: integrated approach

    Publication Year: 2006 , Page(s): 59 - 68
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    Memory-related activity is one of the major sources of energy consumption in embedded systems. Many types of memories used in embedded systems allow multiple operating modes (e.g. active, standby, nap, power-down) to facilitate energy saving. Furthermore, it has been known that the potential energy saving increases when the embedded systems use multiple memory banks in which their operating modes are controlled independently. The authors propose a compiler-directed integrated approach to the problem of maximally utilising the operating modes of multiple memory banks by solving the three important tasks simultaneously: (1) assignment of variables to memory banks, (2) scheduling of memory access operations and (3) determination of operating modes of banks. Specifically, for an instance of tasks 1 and 2, the authors formulate task 3 as a shortest path (SP) problem in a network and solved it optimally. Then, an SP-based heuristic that solves tasks 2 and 3 efficiently in an integrated fashion is developed. Then the proposed approach is extended to address the limited register constraint in the processor. From experiments with a set of benchmark programs, it is confirmed that the proposed approach is able to reduce the energy consumption by 15.76% over that by the conventional approach. View full abstract»

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