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Microwave Theory and Techniques, IEEE Transactions on

Issue 1 • Date Jan. 2006

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  • Table of contents

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  • IEEE Transactions on Microwave Theory and Techniques publication information

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  • IMD reduction in CMOS double-balanced mixer using multibias dual-gate transistors

    Page(s): 4 - 9
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    This paper presents a novel and simple linearization scheme for a CMOS double-balanced mixer based on the use of multibias dual-gate transistors. In this technique, intermodulation-distortion (IMD) components with proper phase relationship, generated by devices operating at different bias conditions, are combined together to improve the linearity of mixers. For experimental verification, the measured performance of a fabricated CMOS mixer is shown. Over 35 dB of IMD reduction is achieved by the proposed method under proper biasing condition. View full abstract»

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  • New miniature 15-20-GHz continuous-phase/amplitude control MMICs using 0.18-μm CMOS technology

    Page(s): 10 - 19
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    The design and performance of two new miniature 360° continuous-phase-control monolithic microwave integrated circuits (MMICs) using the vector sum method are presented. Both are implemented using commercial 0.18-μm CMOS process. The first phase shifter demonstrates all continuous phase and an insertion loss of 8 dB with a 37-dB dynamic range from 15 to 20 GHz. The chip size is 0.95 mm × 0.76 mm. The second phase shifter can achieve all continuous phase and an insertion loss of 16.2 dB with a 38.8-dB dynamic range at the same frequency range. The chip size is 0.71 mm × 0.82 mm. To the best of the authors' knowledge, these circuits are the first demonstration of microwave CMOS phase shifters using the vector sum method with the smallest chip size for all MMIC phase shifters with 360° phase-control range above 5 GHz reported to date. View full abstract»

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  • Design and analysis of CMOS broad-band compact high-linearity modulators for gigabit microwave/millimeter-wave applications

    Page(s): 20 - 30
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    CMOS broad-band compact high-linearity binary phase-shift keying (BPSK) and IQ modulators are proposed and analyzed in this paper. The modulators are constructed utilizing a modified reflection-type topology with the transmission lines implemented on the thick SiO2 layer to avoid the lossy silicon substrate. The monolithic microwave integrated circuit (MMIC) chips were fabricated using standard bulk 0.13-μm MS/RF CMOS process and demonstrated an ultracompact layout with more than 80% chip size reduction. The broadside couplers and 180° hybrid for the modulators in the CMOS process are broad-band designs with low phase/amplitude errors. The dc offset and imbalance for the proposed topology are investigated and compared with the conventional reflection-type modulators. The measured dc offset was improved by more than 10 dB. Both BPSK and IQ modulators feature a conversion loss of 13 dB, a modulation bandwidth of wider than 1 GHz, and second- and third-order spur suppressions of better than -30 dBc. The IQ modulator shows good sideband suppression with high local-oscillator suppression from 20 to 40 GHz. The modulators are also evaluated with a digital modulation signal and demonstrate excellent modulator quality and adjacent channel power ratio. View full abstract»

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  • Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

    Page(s): 31 - 39
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    A low insertion-loss single-pole double-throw switch in a standard 0.18-μm complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P1dB, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P1dB of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P1dB of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm2. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches. View full abstract»

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  • Development of multiband phase shifters in 180-nm RF CMOS technology with active loss compensation

    Page(s): 40 - 45
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    We present the design and development of a novel integrated multiband phase shifter that has an embedded distributed amplifier for loss compensation in 0.18-μm RF CMOS technology. The phase shifter achieves a measured 180° phase tuning range in a 2.4-GHz band and a measured 360° phase tuning range in both 3.5- and 5.8-GHz bands. The gain in the 2.4-GHz band varies from 0.14 to 6.6 dB during phase tuning. The insertion loss varies from -3.7 dB to 5.4-dB gain and -4.5 dB to 2.1-dB gain in the 3.5- and 5.8-GHz bands, respectively. The gain variation can be calibrated by adaptively tuning the bias condition of the embedded amplifier to yield a flat gain during phase tuning. The return loss is less than -10 dB at all conditions. The chip size is 1200 μm×2300 μm including pads. View full abstract»

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  • Distortion in RF CMOS short-channel low-noise amplifiers

    Page(s): 46 - 56
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    An approach to estimate the distortion in CMOS short-channel (e.g. 0.18-μm gate length) RF low-noise amplifiers (LNAs), based on Volterra's series, is presented. Compact and accurate frequency-dependent closed-form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second-order distortion (HD2), in CMOS short-channel based LNAs, is studied. This is crucial for systems such as homodyne receivers. Equations describing third-order intermodulation distortion in RF LNAs are reported. The analytical analysis is verified through simulations and measured results of an 0.18-μm CMOS 5.8-GHz folded-cascode LNA prototype chip geared toward sub-1-V operation. It is shown that the distortion is independent of the gate-source capacitance Cgs of the MOS transistors, allowing an extra degree of freedom in the design of LNA circuits. Distortion-aware design guidelines for RF CMOS LNAs are provided throughout the paper. View full abstract»

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  • Millimeter-wave design considerations for power amplifiers in an SiGe process technology

    Page(s): 57 - 64
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    This paper describes a number of significant modeling considerations for SiGe heterojunction bipolar transistor power amplifiers operating at millimeter-wave frequencies. Small- and large-signal model-to-hardware correlation is presented for single transistor amplifiers, as well as for a combined dual-stage amplifier up to 65 GHz. The relevant parasitic effects are described along with the proposed modeling approach for each of them. The limits of the standard Vertical Bipolar Inter-Company device model at high-injection and their effect on the prediction of the achievable large-signal compression and power-added efficiency are also discussed. View full abstract»

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  • Design of low-power fast VCSEL drivers for high-density links in 90-nm SOI CMOS

    Page(s): 65 - 73
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    The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser drivers a challenging task. Hence, a detailed comparison of three basic driver architectures, namely, common source (CS), CS with source degeneration, and source follower (SF) is presented using transistor models including short channel effects. Based on this comparison, two power-optimized driver topologies are implemented in a 90-nm silicon-on-insulator CMOS technology. The SF driver features a bandwidth of 18 GHz on a 50-Ω load. The required chip area is only 140 μm×140 μm, which is very beneficial for high-density short-distance optical interconnects. This allows a data rate of 12.5 Gb/s at a bit error ratio of less than 10-12 to be achieved even with a 10-Gb/s oxide confined vertical-cavity surface-emitting laser (VCSEL). The power consumption is 27 mW. The drivers were optimized for maximal eye opening by applying a fast and accurate VCSEL model. View full abstract»

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  • Switched resonators and their applications in a dual-band monolithic CMOS LC-tuned VCO

    Page(s): 74 - 81
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    A switched resonator concept, which can be used to reduce the size of multiple-band RF systems and which allows better tradeoff between phase noise and power consumption, is demonstrated using a dual-band voltage-controlled oscillator (VCO) in a 0.18-μm CMOS process. To maximize Q of the switched resonator when the switch is on, the mutual inductance between the inductors should be kept low and the switch transistor size should be optimized. The Q factor of switched resonators is ∼30% lower than that of a standalone inductor. The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of -125 and -123dBc/Hz at a 600-kHz offset and 16-mW power consumption. Compared to a single-band 1.8-GHz VCO, the dual-band VCO has almost the same phase noise and power consumption, while occupying ∼37% smaller area. View full abstract»

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  • An improved model for ground-shielded CMOS test fixtures

    Page(s): 82 - 87
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    An improved model for ground-shielded (GS) test fixtures is proposed. The proposed model provides more accurate device-under-test gap behavioral model than previous test-fixture models and takes into account the impedance of the ground return path. The new model is validated up to 25 GHz by comparing the model simulations with experimental measurements. The proposed model is applied to bulk-silicon- and sapphire-based GS test fixtures with different layouts. Furthermore, a large phase shift in the shield-based test-fixture forward transmission is reported in this study. Based on the results achieved, suggestions for deembedding method selection are given. Test fixtures were fabricated using a 0.35-μm CMOS process and 0.5-μm silicon-on-sapphire CMOS process. View full abstract»

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  • A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

    Page(s): 88 - 95
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (771 KB) |  | HTML iconHTML  

    A downconversion double-balanced oscillator mixer using 0.18-mum CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers View full abstract»

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  • A digitally controlled constant envelope phase-shift modulator for low-power broad-band wireless applications

    Page(s): 96 - 105
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    A low-power constant envelope phase-shift modulator is presented. The circuit switches the phase of a constant amplitude carrier at output according to the input digital data. Design issues and their impact on the performance of the modulator are discussed. A test chip was fabricated in a 0.18-mum CMOS process. Experiment results verified the design principle of the modulator. The modulator consumes 2 mA and is suitable for low-power wireless applications like sensor network and personal area network. Since the circuit is implemented mostly by digital circuit, has broad-band frequency response, and supports high data rate, the modulator can be used at various wireless bands. The measured operating range of carrier frequency is 1.75 to 3.5 GHz, and the modulation data rate can go up to 500 Mb/s. In addition, the modulator can be modified to generate different modulations by digitally controlling both the phase and amplitude of the output signal from a phasor-combining circuit. Therefore, the modulator can potentially be used for software configurable radios View full abstract»

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  • A new set of H(curl)-conforming hierarchical basis functions for tetrahedral meshes

    Page(s): 106 - 114
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    A new set of H(curl)-conforming hierarchical basis functions for tetrahedral meshes is presented. Contrary to previous bases, this one is designed such that higher order basis functions vanish when they are projected onto a lower order finite-element space using the interpolation operator defined by Nedelec. Consequently, to increase the polynomial order and improve the accuracy of the interpolated field, only additional degrees of freedom (DOFs) of higher order are added, whereas the original DOFs (the coefficients for the basis functions) remain unchanged. This makes this basis very well suited for use with efficient multilevel solvers and goal-oriented hierarchical error estimators, which is demonstrated through numerical examples View full abstract»

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  • Characteristic-function approach to parameter extraction for asymmetric equivalent circuit of on-chip spiral inductors

    Page(s): 115 - 119
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    A novel approach to parameter extraction for an asymmetric equivalent circuit of silicon-on-chip spiral inductors based on measured S-parameter is proposed. The current methodology is based on the linear dependence of a set of characteristic functions on other functions or variables such as omega2 in a certain frequency range, and the model parameters can be derived from the corresponding linear coefficients. As applied to an asymmetric single-pi equivalent circuit, the extracted parameters can simulate the inductor with a high precision up to 10 GHz View full abstract»

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  • Design and modeling of 4-bit slow-wave MEMS phase shifters

    Page(s): 120 - 127
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    A true-time-delay multibit microelectromechanical systems (MEMS) phase-shifter topology based on impedance-matched slow-wave coplanar-waveguide sections on a 500-mum-thick quartz substrate is presented. A semilumped model for the unit cell is derived and its equivalent-circuit parameters are extracted from measurement and electromagnetic simulation data. This unit cell model can be cascaded to accurately predict N-section phase-shifter performance. Experimental data for a 4.6-mm-long 4-bit device shows a maximum phase error of 5.5deg and S11 less than -21 dB from 1 to 50 GHz with worst case S21 less than -1.2 dB. In a second design, the slow-wave phase shifter was additionally loaded with MEMS capacitors to result in a phase shift of 257deg/dB at 50 GHz, while keeping S11 below -19 dB (with S21<-1.9 dB). The beams are actuated using high-resistance SiCr bias lines with typical actuation voltage around 30-45 V View full abstract»

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  • A full-duplex dual-frequency self-steering array using phase detection and phase shifting

    Page(s): 128 - 134
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    A full-duplex dual-frequency self-steering array using phase detection and phase shifting is presented. By RF decoupling the transmitter and receiver arrays, the proposed system promises greater system efficiency by ensuring a constant transmit power. This also allows for a separate low-frequency interrogating signal capable of various modulation schemes. A two-element prototype is demonstrated with interrogating and retrodirective frequencies of 1.425 and 2.85 GHz, respectively. Retrodirectivity is reported for angles of 0deg, -15deg, and +25deg. The power of the received signal is improved by up to 12 dB for -60deglesthetasles60deg when compared to a conventional two-element array View full abstract»

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  • A substrate for small patch antennas providing tunable miniaturization factors

    Page(s): 135 - 146
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    Magnetic properties were imparted to a naturally nonmagnetic material by metallic inclusions. A patch antenna tested the performance of the magnetic metamaterial as a substrate and validated that a single substrate can achieve a range of miniaturization values. The effective medium metamaterial substrate employed electromagnetically small embedded circuits (ECs) to achieve permeability and permittivity greater than that of the host dielectric. Geometric control of the ECs allowed mu and epsi to be tailored to the application. The magnetic metamaterial exhibited enhanced mu and epsi with acceptable loss-factor levels. Models for predicting mu and epsi are presented, the benefits of employing metamaterial substrates are discussed, and the results in this antenna experiment are presented. The metamaterial exhibits performance characteristics not achievable from natural materials. Of particular significance is that with the permeability varying strongly and predictably with frequency, the miniaturization factor may be selected by tuning the operating frequency. Simulations indicate that such performance can be extended to several gigahertz with current technology. Relative permeability values in the mur=1-5 range are achievable for moderately low-loss applications. Representative antenna miniaturization factors on the order of 4-7 over a moderate (approximately 10%) transmission bandwidth and efficiencies in a moderate range (20%-35%) are demonstrated with the possibility of higher efficiencies indicated View full abstract»

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  • Hybrid rectenna and monolithic integrated zero-bias microwave rectifier

    Page(s): 147 - 152
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    In this study, we have developed a hybrid sensitive rectenna (rectifier + antenna) system at 2.45 GHz. To achieve this system, we have first optimized and validated a zero-bias microwave sensitive rectifier using commercial Schottky diodes. We have then optimized and achieved a 2times2 patch antenna array, which is associated to the microwave rectifier in order to validate the rectenna system, where an RF-dc conversion efficiency of 56% has been observed experimentally. In order to minimize the rectenna dimensions, we have conducted a study using the OMMIC ED02AH 0.20-mum GaAs pseudomorphic high electron-mobility transistor process to develop and achieve a monolithic rectifier at 2.45 GHz with RF-dc conversion efficiency of 65% View full abstract»

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  • On the conception and analysis of a 12-GHz push-push phase-locked DRO

    Page(s): 153 - 159
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    This paper describes the design and behavior of a 12-GHz push-push dielectric resonator oscillator in a phase-locked environment. This phase-locked dielectric resonator oscillator (PLDRO) differs from conventional designs on many fronts. First, it uses a push-push oscillator for its improved phase noise and reduced fundamental frequency. Second, the phase detection is implemented at a 3-GHz IF as an alternative to detecting at RF using a sampling phase detector (PD). Finally, the push-push PLDRO is tuned via coupled microstrip lines to minimize oscillator loading. These modifications are intended to minimize the risk of PLDRO lock failures by maintaining a constant PD gain via amplifiers operating at P1dB, and by halving the DRO fundamental frequency using the push-push approach. Experimental results indicate a fundamental suppression of 27 dBc, and single-sideband phase noise densities of -105, -110, and -125 dBc/Hz at 10-kHz, 100-kHz, and 1-MHz offsets, respectively, from a 12-GHz carrier View full abstract»

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  • Compact microstrip dual-band bandpass filters design using genetic-algorithm techniques

    Page(s): 160 - 168
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    An optimization scheme based on hybrid-coded genetic-algorithm (GA) techniques is presented to design compact dual-band bandpass filters with microstrip lines. A representation scheme is proposed to represent an arbitrary microstrip circuit as a set of data structures. Each data structure in the set describes a simple two-port network with the corresponding connection method and electrical parameters. The optimization algorithm based on conventional GAs is then applied to simultaneously search for the appropriate circuit topology and the corresponding electrical parameters with dual-band characteristic. Two examples are designed and implemented to validate the proposed algorithm. In the first example, the 3-dB fractional bandwidth of the low and high bands is 35% and 17%, respectively. It has return losses larger than 10 dB from 2.14 to 2.96 and 5.14 to 6.06 GHz. In the second example, the 3-dB fractional bandwidth of the low and high bands is 9.9% and 7.9%, respectively. The return losses are larger than 10 dB from 3.37 to 3.64 and 5.27 to 5.62 GHz. The sizes of the proposed filters are nearly half as small as those of the filters presented before. All the studies are completed on a computer with a 2.4-GHz microprocessor, and the computing time of two examples is 6 and 3 min, respectively View full abstract»

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  • An evaluation of three simple scalable MIM capacitor models

    Page(s): 169 - 172
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    This paper presents an evaluation of three different scalable metal-insulator-metal capacitor models for use in monolithic-microwave integrated-circuit design. The models, including one previously unpublished, are based on transmission-line theory and are easily scalable using only physical dimensions and constants. Comparisons to measured data for several device sizes, up to 45deg in electrical length, show that the three models exhibit similar performance, with a mean deviation between models and S11 measurements that is less than 3% View full abstract»

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  • Full-wave nonlinear analysis of nonradiative dielectric guide circuits including lumped elements

    Page(s): 173 - 179
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    This paper describes the full-wave numerical analysis of complex nonradiative dielectric (NRD) guide structures including linear or nonlinear lumped elements. The numerical results described in this paper, validated through experimentation, show that the method is suitable for NRD guide and similar circuits. Nonlinear analysis of a single-ended NRD guide mixer is carried out, and the results are experimentally verified. Nonlinear harmonic-balance analysis of a novel leaky-wave balanced mixer circuit with very good tolerance of manufacturing inaccuracies in NRD guide configuration in Ka-band is then carried out. Due to curved segments, and orders of magnitude difference in the dimensions of different parts, the analysis of this component requires certain simplifying assumptions. How these can be implemented without sacrificing much accuracy is described. Until now, the design of NRD guide components, especially those using nonlinear effects, has been mostly trial-and-error-based. Here we demonstrate that a more systematic approach is possible View full abstract»

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Aims & Scope

The IEEE Transactions on Microwave Theory and Techniques focuses on that part of engineering and theory associated with microwave/millimeter-wave components, devices, circuits, and systems involving the generation, modulation, demodulation, control, transmission, and detection of microwave signals. This includes scientific, technical, and industrial, activities. Microwave theory and techniques relates to electromagnetic waves usually in the frequency region between a few MHz and a THz; other spectral regions and wave types are included within the scope of the Society whenever basic microwave theory and techniques can yield useful results. Generally, this occurs in the theory of wave propagation in structures with dimensions comparable to a wavelength, and in the related techniques for analysis and design..

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