IEEE Transactions on Computers

Issue 2 • Feb. 2006

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Displaying Results 1 - 17 of 17
  • [Front cover]

    Publication Year: 2006, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2006, Page(s): c2
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  • Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC)

    Publication Year: 2006, Page(s):97 - 98
    Cited by:  Papers (2)
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  • A systematic approach to exploring embedded system architectures at multiple abstraction levels

    Publication Year: 2006, Page(s):99 - 112
    Cited by:  Papers (173)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1144 KB) | HTML iconHTML

    The sheer complexity of today's embedded systems forces designers to start with modeling and simulating system components and their interactions in the very early design stages. It is therefore imperative to have good tools for exploring a wide range of design choices, especially during the early design stages, where the design space is at its largest. This paper presents an overview of the Sesame... View full abstract»

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  • Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

    Publication Year: 2006, Page(s):113 - 124
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1192 KB) | HTML iconHTML

    We have previously demonstrated that use of an appropriate dynamic voltage scaling (DVS) algorithm can lead to a substantial reduction in CPU power consumption in systems employing a time-triggered cooperative (TTC) scheduler. In this paper, we consider the impact that the use of DVS has on the levels of both clock and task jitter in TTC applications. We go on to describe a modified DVS algorithm ... View full abstract»

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  • Enhancing performance of HW/SW cosimulation and coemulation by reducing communication overhead

    Publication Year: 2006, Page(s):125 - 136
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1464 KB) | HTML iconHTML

    For system-level simulation of a complex system-on-chip design, multiple hardware simulators and emulators can be combined to work together. The simulation performance in this case is often limited by the communication overhead between simulators and emulators. To reduce the amount of communication in this heterogeneous simulation environment, we propose novel methods to find a time interval durin... View full abstract»

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  • InTeRail: a test architecture for core-based SOCs

    Publication Year: 2006, Page(s):137 - 149
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2136 KB) | HTML iconHTML

    A flexible test architecture for embedded cores and all interconnects in a system-on chip (SOC) is presented. It targets core testing parallelism and reduced test application time by using, as much as possible, existing core interconnects to form TAM paths. It also provides for dynamic wrapper reconfiguration. Algorithms that minimize the use of extra interconnects for the TAM path formation are p... View full abstract»

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  • Testing embedded sequential cores in parallel using spectrum-based BIST

    Publication Year: 2006, Page(s):150 - 162
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1248 KB) | HTML iconHTML

    We present a new BIST (built-in-self-test) architecture for system-on-a-chip (SOC), which can test a cluster of embedded sequential cores simultaneously. The compressed spectrum for a cluster of cores under test is computed by performing spectral analysis individually on all cores. Because there is no need to combine the cores to extract the spectrum for the entire cluster, the computation complex... View full abstract»

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  • XPAND: an efficient test stimulus compression technique

    Publication Year: 2006, Page(s):163 - 173
    Cited by:  Papers (58)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB) | HTML iconHTML

    Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from compressed seeds. Unlike major test compression techniques, this technique doesn't require test pattern generation with don't cares. Experimental results on industrial designs demonstrate that this new XPAND technique achieves exponential reduction in test data volume and ... View full abstract»

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  • Debug support strategy for systems-on-chips with multiple processor cores

    Publication Year: 2006, Page(s):174 - 184
    Cited by:  Papers (49)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB) | HTML iconHTML

    On-chip program and data tracing is now an essential part of any system level development platform for system-on-chip (SoC). Current debug support solutions are platform specific and incompatible with processors and active peripherals from other sources, restricting effective design reuse. In order to overcome this reuse challenge, this paper defines interfaces to decouple the debug support from p... View full abstract»

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  • A new hybrid fault detection technique for systems-on-a-chip

    Publication Year: 2006, Page(s):185 - 198
    Cited by:  Papers (44)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1248 KB) | HTML iconHTML

    Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or ) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastruct... View full abstract»

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  • Dynamic resizing of superscalar datapath components for energy efficiency

    Publication Year: 2006, Page(s):199 - 213
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1568 KB) | HTML iconHTML

    The "one-size-fits-all" philosophy used for permanently allocating datapath resources in today's superscalar CPUs to maximize performance across a wide range of applications results in the overcommitment of resources in general. To reduce power dissipation in the datapath, the resource allocations can be dynamically adjusted based on the demands of applications. We propose a mechanism to dynamical... View full abstract»

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  • Global clock synchronization in sensor networks

    Publication Year: 2006, Page(s):214 - 226
    Cited by:  Papers (178)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB) | HTML iconHTML

    Global synchronization is important for many sensor network applications that require precise mapping of collected sensor data with the time of the events, for example, in tracking and surveillance. It also plays an important role in energy conservation in MAC layer protocols. This paper describes four methods to achieve global synchronization in a sensor network: a node-based approach, a hierarch... View full abstract»

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  • Power-aware test planning in the early system-on-chip design exploration process

    Publication Year: 2006, Page(s):227 - 239
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1624 KB) | HTML iconHTML

    Test application and test design, performed to ensure the production of fault-free chips, are becoming complicated and very expensive, especially in the case of SoCs (system-on-chip), as the number of possible faults in a chip is increasing dramatically due to the technology development. It is therefore important to take test design into consideration as early as possible in the SoC design-flow in... View full abstract»

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  • [Advertisement]

    Publication Year: 2006, Page(s): 240
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  • TC Information for authors

    Publication Year: 2006, Page(s): c3
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  • [Back cover]

    Publication Year: 2006, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org