Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Issue 11 • Date Nov. 2005
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Table of contents
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information
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Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation
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Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
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Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations
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Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors
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Aims & Scope
IEEE Transactions on Very Large Scale Integration (VLSI) Systems includes all major aspects of the design and implementation of VLSI/ULSI and microelectronic systems.
Meet Our Editors
Editor-in-Chief
Yehea Ismail
CND Director
American University of Cairo and Zewail City of Science and Technology
New Cairo, Egypt
tvlsieic@eecs.northwestern.edu
