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Electron Devices, IEEE Transactions on

Issue 1 • Date Jan. 2006

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Displaying Results 1 - 25 of 32
  • Table of contents

    Page(s): c1 - c4
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  • IEEE Transactions on Electron Devices publication information

    Page(s): c2
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  • Influences of sulfur passivation on temperature-dependent characteristics of an AlGaAs/InGaAs/GaAs PHEMT

    Page(s): 1 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB) |  | HTML iconHTML  

    The influences of (NH4)2Sx treatment on an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) are studied and demonstrated. Upon the sulfur passivation, the studied device exhibits better temperature-dependent dc and microwave characteristics. Experimentally, for a 1×100 μm2 gate/dimension PHEMT with sulfur passivation, the higher gate/drain breakdown voltage of 36.4 (21.5) V, higher turn-on voltage of 0.994 (0.69) V, lower gate leakage current of 0.6 (571) μA/mm at VGD=-22 V, improved threshold voltage of -1.62 (-1.71) V, higher maximum transconductance of 240 (211) mS/mm with 348 (242) mA/mm broad operating regime (>0.9gm,max), and lower output conductance of 0.51 (0.53) mS/mm are obtained, respectively, at 300 (510) K. The corresponding unity current gain cutoff frequency fT (maximum oscillation frequency fmax) are 22.2 (87.9) and 19.5 (59.3) GHz at 250 and 400 K, respectively, with considerably broad operating regimes (>0.8fT,fmax) larger than 455 mA/mm. Moreover, the relatively lower variations of device performances over wide temperature range (300∼510 K) are observed. View full abstract»

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  • Engineering density of semiconductor-dielectric interface states to modulate threshold voltage in OFETs

    Page(s): 9 - 13
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    Threshold-voltage control is critical to the further development of pentacene organic field-effect transistors (OFETs). In this paper, we demonstrate that the threshold voltage can be tuned through chemical treatment of the gate dielectric layer. We show that oxygen plasma treatment of an organic polymer gate dielectric, parylene, introduces traps at the semiconductor-dielectric interface that strongly affect the OFET performance. Atomic force microscopy, optical microscopy using crossed-polarizers, and current-voltage and capacitance-voltage characterization were performed on treated and untreated devices. A model is presented to account for the effects of trap-introduced charges, both 1) fixed charges (2.0×10-6 C/cm2) that shift the threshold voltage from -17 to +116 V and 2) mobile charges (1.1×10-6 C/cm2) that increase the parasitic bulk conductivity. This technique offers a potential method of tuning threshold voltage at the process level. View full abstract»

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  • A three charge-states model for silicon nanocrystals nonvolatile memories

    Page(s): 14 - 22
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    In the field of nonvolatile memories, substantial improvement of reliability is obtained by replacing the continuous polysilicon floating gate by a planar distribution of silicon nanocrystals, each acting as a storage node. The test devices in the present paper are MOS capacitors containing a two-dimensional layer of nanocrystals located 2.5 nm away from the oxide/substrate interface, inside the SiO2. This work presents various measurements of the charge current versus either bias voltage or time. On the other side, the charge and discharge dynamics of the nanocrystals had already been described by De Salvo using a model borrowed from the conventional floating-gate memory. We show this approach to be not completely suitable to explain the experimental observations. Thus, we describe and apply a so-called granular model, based on a mono-electronic principle limited by Coulomb blockade, in which electrons interact with the nanocrystals one by one. Omitting the reality of such a one-by-one principle may involve important mistakes in the interpretation of phenomena. View full abstract»

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  • Interpretation of current flow in photodiode structures using laser beam-induced current for characterization and diagnostics

    Page(s): 23 - 31
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    This paper presents an interpretation of the physical mechanisms involved in the generation of laser beam-induced current (LBIC) in semiconductor p-n junction diodes. LBIC is a nondestructive semiconductor characterization technique that has been used in a qualitative manner for a number of years and is especially useful for examining individual photodiodes within large two-dimensional arrays of devices. The main thrust of this work is the analysis of LBIC in terms of nonzero steady-state circulatory current flow within the device and, hence, the interpretation of LBIC line profiles to diagnose the patterns of current flow within the structure. This provides an important basis for future studies seeking to relate LBIC to indicators of p-n junction performance and integrity such as dark current components and reverse bias saturation current. In particular, this paper examines the ideal cases of a single isolated p-n junction diode structure, and also considers an array of such devices in close proximity to each other. Modifications to the idealized theory that are required to account for localized junction leakage and surface recombination are presented, and the effect of Schottky contacts is discussed. Numerical simulations based on the HgCdTe family of semiconductors are presented to support the theory. View full abstract»

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  • Rapid thermal annealed InGaN/GaN flip-chip LEDs

    Page(s): 32 - 37
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    Nitride-based flip-chip (FC) light-emitting diodes (LEDs) emitting at 465 nm with Ni transparent ohmic contact layers and Ag reflective mirrors were fabricated. With an incident light wavelength of 465 nm, it was found that transmittance of normalized 300°C rapid thermal annealed (RTA) Ni(2.5 nm) was 93% while normalized reflectance of 300°C RTA Ni(2.5 nm)/Ag(200 nm) was 92%. It was also found that 300°C RTA Ni(2.5 nm) formed good ohmic contact on n+ short-period-superlattice structure with specific contact resistance of 7.8×10-4 Ω·cm2. With 20-mA current injection, it was found that forward voltage and output power were 3.15 V and 16.2 mW for FC LED with 300°C RTA Ni(2.5 nm)/Ag(200 nm). Furthermore, it was found that reliabilities of FC LEDs were good. View full abstract»

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  • GaN MSM UV photodetectors with titanium tungsten transparent electrodes

    Page(s): 38 - 42
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    GaN metal-semiconductor-metal (MSM) ultraviolet photodetectors with titanium tungsten (TiW) transparent electrodes were fabricated and characterized. It was found that the 10-nm-thick TiW film deposited with a 300-W RF power can still provide a reasonably high transmittance of 75.1% at 300 nm, a low resistivity of 1.7×10-3 Ω·cm and an effective Schottky barrier height of 0.773 eV on u-GaN. We also achieved a peak responsivity of 0.192 A/W and a quantum efficiency of 66.4% from the GaN ultraviolet MSM photodetector with TiW electrodes. With a 3-V applied bias, it was found that minimum noise equivalent power and maximum D* of our detector were 1.987×10-10 W and 6.365×109 cmHz0.5W-1, respectively. View full abstract»

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  • Hot-carrier-induced degradation of LDD polysilicon TFTs

    Page(s): 43 - 50
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    In order to improve the stability of polysilicon thin-film transistors (TFTs) several drain junction architectures have been proposed. In this paper, the hot-carrier (HC) related stability of the lightly doped drain (LDD) TFT architecture is analyzed by using an iterative algorithm that relates the HC induced damage to the carrier injection across the device interfaces with gate and substrate oxide. The resulting creation of interface states and trapped charge is taken into account by using a system of rate equations that implements mathematically the Lais two step model, in which the generation of interface states is attributed to the trapping of hot-holes by centres into the oxide followed by the recombination with hot electrons. The rate equations are solved self-consistently with the aid of a device simulation program. By successive iterations, the time evolution of the interface state density and positive trapped charge distribution has been reconstructed, and the electrical characteristics calculated with this model are in good agreement with experimental data. This algorithm represent an improvement of an already proposed degradation model, in which the interface states formation dynamics is accounted by using a phenomenological approach. The present model has been applied to reproduce the degradation pattern of LDD TFTs and it is found that generation of interface states proceed almost symmetrically on the front and back device interfaces, starting from the points in which the transverse electric field peaks, and moving toward the drain side of the device. The final interface states distribution determines a sort of "bottleneck" in the active layer carrier density, that can explain the sensitivity to HC induced damage of both transfer and output characteristics. View full abstract»

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  • Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

    Page(s): 51 - 55
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    Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current. View full abstract»

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  • HSPICE macromodel of PCRAM for binary and multilevel storage

    Page(s): 56 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    A general macromodel of the phase change random access memory (PCRAM) elements for use in HSPICE-based computer simulator is proposed in this paper by introducing physical models of PCRAM elements. It can simulate the dc and transient behavior of PCRAM element. In this paper, the model was integrated with the standard R/W circuit and successfully simulated the R-I curve and dependence between amplitude and width of programming pulses. A comparison between experimental and simulation results were also given. Furthermore, by including the partial crystallization states, the macromodel was developed for simulating the multilevel storage. View full abstract»

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  • Effects of interstitial oxygen defects at HfOxNy/Si interface on electrical characteristics of MOS devices

    Page(s): 63 - 70
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    Effects of the defects at high-κ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfOxNy demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [Oi] and the crystal-originated particles defects as well as small surface roughness at HfOxNy/Si interface. The current-conduction mechanism of the HfOxNy film at the low- and high-electrical field and high-temperature (T>100°C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfOxNy/Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (Dit). The results exhibit that relatively low Dit can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfOxNy has demonstrated significant improvement on electrical properties as compared to SiOxNy. View full abstract»

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  • Boron pocket and channel deactivation in nMOS transistors with SPER junctions

    Page(s): 71 - 77
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    In this paper, we demonstrate the consequences of extension junction formation by low-temperature solid-phase-epitaxial-regrowth in nMOS transistors. Atomistic simulations, experimental device results, sheet resistance, and scanning spreading resistance microscopy data indicate that the high concentration of silicon interstitials associated with the end-of-range defect band promote the local formation of boron-interstitial clusters, and thus deactivate boron in the pocket and channel. These inactive clusters will dissolve after the high concentration silicon interstitial region of the end-of-range defect band has been annihilated. This nMOS requirement is in direct opposition to the pMOS case where avoidance of defect band dissolution is desired, to prevent deactivation of the high concentration boron extension profile. View full abstract»

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  • A novel high-κ SONOS memory using TaN/Al2O3/Ta2O5/HfO2/Si structure for fast speed and long retention operation

    Page(s): 78 - 82
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    A novel high-κ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al2O3/Ta2O5/HfO2/Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO2/Ta2O5/HfO2/Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO2) with aluminum oxide (Al2O3) for the top blocking layer, better blocking efficiency can be achieved due to Al2O3's much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 105 stress cycles at a tunnel oxide of only 9.5 Å equivalent oxide thickness. View full abstract»

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  • An effective single-trap-level model for the proton-induced semi-insulating substrates

    Page(s): 83 - 88
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    To suppress the undesirable substrate couplings, a novel approach, called the π technology (particle-enhanced isolation), was previously proposed, in which energetic proton beams were applied on the already-manufactured mixed-mode IC wafers prior to their packaging . The results of an improvement of 25-30 dB in coupling reduction and a two-to-three folds enhancement in inductor Q values were also demonstrated. The continuing improvement of this π technology has shed light on the concept of a new very large-scale integration backend solution: the particle-beam stand, a brute-force that may ultimately bring general system-on-a-chip manufacturing to a common platform. However, up to this day the physics describing properties of such proton-caused defect phase has never emerged. In this paper, the possible establishment of an effective, self-consistent, single level defect model is attempted. It will be carried out by fitting the existing single-trap-level theory with experimentally obtained parameters and the data from numerical simulations using the the stopping and range of ions in matter code (a charged-particle stopping-power calculation program). It will be revealed that, more than mere simple traps of charge carriers, those proton-created defects were also intrinsically charged (carrying +e or -e) and thus all were participating in the Rutherford-like scattering of the remaining free charge carriers which had survived the defect trapping. The calculated effective single trap level (ET) is about +0.24 eV in n-Si and -0.34 eV in p-Si, measuring from the center of the energy bandgap. View full abstract»

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  • Monte Carlo simulation of substrate enhanced electron injection in split-gate memory cells

    Page(s): 89 - 96
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    In this paper, we use fullband Monte Carlo simulations and gate current measurements to investigate charge injection in split-gate memory cells under negative substrate bias. It is shown that, in the source-side-injection (SSI) regime, the enhancement of the programming efficiency due to the substrate bias is low, unless very low drain and floating-gate biases are considered. In particular, the enhancement of the efficiency is largely reduced if the drain current is kept constant when comparing different substrate biases. Furthermore, it is observed that the carrier injection profile under negative substrate bias is broader than in the SSI regime, and a substantial amount of charge is injected in the spacer region. View full abstract»

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  • Impact of high tunneling electric fields on erasing instabilities in NOR flash memories

    Page(s): 97 - 102
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    Experimental data and analysis show that overerase effects in NOR Flash memories increase with the electric field used during erasing. We found that the electric field is an accelerating factor for cell degradation during cycling. Tunnel oxide degradation reaches a critical level above which the cell starts showing erased threshold voltage instabilities possibly leading to single bit failure. Experimental data show that cell degradation during erasing has to be ascribed to hole injection rather than to electron injection and that both hole trapping and detrapping increase with the electric field. The total stress time required to reach the critical degradation level has been found to follow a 1/Eox exponential dependence which is similar to the oxide breakdown phenomena thus establishing a physical link between the two phenomena. Anode Hole Injection has been suggested as hole generation and injection mechanism occurring during erasing and it is shown to be consistent with the experimental data. View full abstract»

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  • Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique

    Page(s): 103 - 108
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    In this paper, we use a modified charge pumping technique to characterize the programmed charge lateral distribution in a hot electron program/hot hole erase, two-bit storage nitride Flash memory cell. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the second programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases. View full abstract»

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  • Highly scalable ballistic injection AND-type (BiAND) flash memory

    Page(s): 109 - 111
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    An AND-type split-gate Flash memory cell with a trench select gate and a buried n+ source is proposed. This cell, programmed by ballistic source side injection (BSSI), can provide high programming efficiency with a cell size of 5F2. Furthermore, both the programming speed and the read current are enhanced by the shared select gate configuration. View full abstract»

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  • Parameterized SPICE model for a phase-change RAM device

    Page(s): 112 - 118
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    A simple form of a SPICE macro model for a generic phase-change random access memory device is presented. The approach is based upon lumped parameter multiple level models. The SPICE implementation is described using a series of increasingly complex modeling blocks for dc to transient analysis. The effect of nonlinear phase switching during the programming cycle is demonstrated in a SPICE simulation and compared to experimental data. View full abstract»

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  • Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model

    Page(s): 119 - 125
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    The reverse read method and second-bit effect of the 2-bit/cell nitride-trapping device are comprehensively studied by a quasi-two-dimensional (2-D) model. Based on this model, analytical equations are derived to simulate the surface potential of the device with locally injected electrons. This model indicates that the reverse read method exploits the local drain-induced barrier lowering (DIBL) effect that reduces the potential barrier produced by the locally injected electrons. The experimental results of the two-region behavior of second-bit effect can be well explained and simulated by this analytical model. Two-dimensional numerical calculations are also carried out to verify these analytical equations. The impact of short-channel effect on the second-bit effect is also examined. View full abstract»

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  • Characterization of oxide trap energy by analysis of the SILC roll-off regime in flash memories

    Page(s): 126 - 134
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    We present a novel experimental technique to identify the energy of traps responsible for the stress-induced leakage current (SILC) in Flash memories, based on a standard gate-stress analysis with a drain bias used to accelerate channel electrons. From the study of the rolloff in SILC characteristics, we provide evidence for the existence of high-energy traps in the silicon dioxide, located at energies above the silicon conduction band minimum. The new technique is able to characterize the position of defects along the channel and the electron effective temperature at the SILC spot, allowing to extract the dependence of channel electron temperature on the distance from the drain. View full abstract»

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  • Loop-based inductance extraction and modeling for multiconductor on-chip interconnects

    Page(s): 135 - 145
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    An efficient extraction and modeling methodology for self and mutual inductances within multiconductors for on-chip interconnects is investigated. The method is based on physical layout considerations and current distribution on multiple return paths, leading to loop inductance and resistance. It provides a lumped circuit model suitable for timing analysis in any circuit simulator, which can represent frequency-dependent characteristics. This novel modeling methodology accurately provides the mutual inductance and resistance as well as self terms within a wide frequency range without using any fitting algorithm. Measurement results for single and coupled wires within a multiconductor system, fabricated using 0.13 and 0.18 μm CMOS technologies, confirm the validity of the proposed method. Our methodology can be applicable to high-speed global interconnects for post-layout as well as prelayout extraction and modeling. View full abstract»

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  • Improved short-channel FET performance with virtual extensions

    Page(s): 146 - 152
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    Here, for the first time, a method is presented to use electrostatic coupling from a metal of appropriate workfunction, separated from the extension region by a thin insulator, to create an electrostatically-induced charge layer in doped source/drain CMOS. This "virtual extension" allows for lower extension doping and increased underlap between the doped extension and the gate, "sharpening" the carrier profile and improving short-channel device performance. In one example, clock-limiting n-FET switching currents are improved 25% using this approach. However, the improvement in switching speed due to this higher current is partially offset by capacitance between the metal overlap and the extension. View full abstract»

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  • Impact of downscaling and poly-gate depletion on the RF noise parameters of advanced nMOS transistors

    Page(s): 153 - 157
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    For the first time, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed. Based on measurements and physical device simulations we quantify the increasing danger of poly gate depletion with downscaling on the RF noise parameters of CMOS devices. While poly depletion does not affect the minimum noise figure, it results in a degradation of the noise matching freedom for RFIC designers. This trend worsens with technology downscaling. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology