Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Issue 10 • Date Oct. 2005
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Table of contents
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information
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Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints
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Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs
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Soft errors issues in low-power caches
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PDF (607 KB)
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Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications
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An energy-aware active smart card
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PDF (732 KB)
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Estimation of FMAX and ISB in microprocessors
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PDF (418 KB)
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006)
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PDF (861 KB)
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IEEE order form for reprints
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors
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Aims & Scope
IEEE Transactions on Very Large Scale Integration (VLSI) Systems includes all major aspects of the design and implementation of VLSI/ULSI and microelectronic systems.
Meet Our Editors
Editor-in-Chief
Yehea Ismail
CND Director
American University of Cairo and Zewail City of Science and Technology
New Cairo, Egypt
tvlsieic@eecs.northwestern.edu
