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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 10 • Date Oct. 2005

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Displaying Results 1 - 16 of 16
  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2005, Page(s): c2
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  • Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

    Publication Year: 2005, Page(s):1113 - 1126
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (924 KB) | HTML iconHTML

    Scheduling and binding are two tasks found in high-level synthesis of hardware as well as in compiling software. These tasks are realized on graphs that are models of the hardware or of the software to be compiled to run on a specific processor. Scheduling focuses on determining the start execution time of each node in the graph. Binding is the task of assigning each node in the graph to a specifi... View full abstract»

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  • Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs

    Publication Year: 2005, Page(s):1127 - 1135
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (591 KB) | HTML iconHTML

    This paper presents a novel formalized technique for variable tapered buffer design achieving Pareto optimal energy-delay tradeoffs. Our main focus lies on the drivers typically found in embedded SRAMs. Much work has been done for variable tapered buffer design explicitly targeting energy (and/or area) tradeoffs for a given target delay. In contrast, the formalized techniques presented here are ca... View full abstract»

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  • Compiler-guided leakage optimization for banked scratch-pad memories

    Publication Year: 2005, Page(s):1136 - 1146
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB) | HTML iconHTML

    Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasin... View full abstract»

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  • Quantitative analysis and optimization techniques for on-chip cache leakage power

    Publication Year: 2005, Page(s):1147 - 1156
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (581 KB) | HTML iconHTML

    On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In nanometer-scale technology, the subthreshold leakage power is becoming one of the dominant total power consumption components of those caches. In this study, we present optimization techniques to reduce the subthreshold leakage power of on-chip caches assuming that there are multiple thresh... View full abstract»

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  • Soft errors issues in low-power caches

    Publication Year: 2005, Page(s):1157 - 1166
    Cited by:  Papers (35)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (607 KB) | HTML iconHTML

    As technology scales, reducing leakage power and improving reliability of data stored in memory cells is both important and challenging. While lower threshold voltages increase leakage, lower supply voltages and smaller nodal capacitances reduce energy consumption but increase soft errors rates. In this work, we present a comprehensive study of soft error rates on low-power cache design. First, we... View full abstract»

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  • Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications

    Publication Year: 2005, Page(s):1167 - 1178
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1252 KB) | HTML iconHTML

    A hybrid two-dimensional position sensing system is designed with microelectromechanical systems (MEMS) for padless mouse applications. The X/Y-axis acceleration of the user's hand movements is measured by two MEMS accelerometer devices. These acceleration values are pulsewidth modulated and converted into (X, Y) coordinates on the screen by integral operations on a microprocessor. The overall sys... View full abstract»

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  • A computationally efficient engine for flexible intrusion detection

    Publication Year: 2005, Page(s):1179 - 1189
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    Pattern matching for network security and intrusion detection demands exceptionally high performance. This paper describes a novel systolic array-based string matching architecture using a buffered, two-comparator variation of the Knuth-Morris-Pratt (KMP) algorithm. The architecture compares favorably with the state-of-the-art hardwired designs while providing on-the-fly reconfiguration, efficient... View full abstract»

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  • An energy-aware active smart card

    Publication Year: 2005, Page(s):1190 - 1199
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB) | HTML iconHTML

    Despite recent advances in smart card technology, most modern smart cards continue to rely on card readers for power and clocking, creating a potential security gap. In this paper, we present an energy-aware smart card architecture that operates using an embedded battery and crystal. This low-power VLSI system is continually active and provides enhanced security through periodic internal update wh... View full abstract»

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  • Extracting secret keys from integrated circuits

    Publication Year: 2005, Page(s):1200 - 1205
    Cited by:  Papers (170)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB) | HTML iconHTML

    Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from conditional access systems such as smartcards and ATMs. Arbiter-based physical unclonable functions (PUFs) exploit the statistical delay variation of wires and tr... View full abstract»

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  • Estimation of FMAX and ISB in microprocessors

    Publication Year: 2005, Page(s):1205 - 1209
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (418 KB) | HTML iconHTML

    Inherent process device variations and fluctuations during manufacturing have a large impact on the microprocessor maximum clock frequency and total leakage power. These fluctuations have a statistical distribution that calls for usage of statistical methods for frequency and leakage analysis. This paper presents a simple technique for accurate estimation of product high-level (Full Chip) paramete... View full abstract»

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  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006)

    Publication Year: 2005, Page(s):1210 - 1211
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  • IEEE order form for reprints

    Publication Year: 2005, Page(s): 1212
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu