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Solid-State Circuits, IEEE Journal of

Issue 12 • Date Dec. 2005

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Displaying Results 1 - 25 of 54
  • [Front cover]

    Publication Year: 2005 , Page(s): c1 - c4
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    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits publication information

    Publication Year: 2005 , Page(s): c2
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  • Table of contents

    Publication Year: 2005 , Page(s): 2357 - 2358
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  • Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference

    Publication Year: 2005 , Page(s): 2359 - 2363
    Cited by:  Patents (1)
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  • A very high precision 500-nA CMOS floating-gate analog voltage reference

    Publication Year: 2005 , Page(s): 2364 - 2372
    Cited by:  Papers (18)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1112 KB) |  | HTML iconHTML  

    A floating gate with stored charge technique has been used to implement a precision voltage reference achieving a temperature coefficient (TC) <1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate analog voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E2PROM CMOS technology. View full abstract»

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  • 0.5-V analog circuit techniques and their application in OTA and filter design

    Publication Year: 2005 , Page(s): 2373 - 2387
    Cited by:  Papers (135)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1728 KB) |  | HTML iconHTML  

    We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-μm CMOS process using standard 0.5-V VT devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 μW. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 μW. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-μm CMOS process with VT of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm2 chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply. View full abstract»

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  • Integrated stereo ΔΣ class D amplifier

    Publication Year: 2005 , Page(s): 2388 - 2397
    Cited by:  Papers (42)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1224 KB) |  | HTML iconHTML  

    A 2×40 W class D amplifier chip is realized in 0.6-μm BCDMOS technology, integrating two delta-sigma (ΔΣ) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency. View full abstract»

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  • A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

    Publication Year: 2005 , Page(s): 2398 - 2407
    Cited by:  Papers (46)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1168 KB) |  | HTML iconHTML  

    A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mm2 using a 0.35-μm CMOS technology. View full abstract»

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  • A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio

    Publication Year: 2005 , Page(s): 2408 - 2415
    Cited by:  Papers (32)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1032 KB) |  | HTML iconHTML  

    An audio ΣΔ analog-to-digital converter (ADC) with the loop filter implemented by continuous-time (CT) and discrete-time (DT) circuits is presented. A tuning circuit is used to compensate for changes in the RC product due to process skew, power supply, temperature and sampling rate variation. To eliminate errors caused by inter-symbol interference (ISI) in the CT feedback DAC, a return-to-zero (RTZ) switching scheme is applied on the error current of the CT integrator. The converter is fabricated in a 0.35-μm CMOS process, and achieves 106-dB dynamic range, -99-dB THD+N. View full abstract»

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  • A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS

    Publication Year: 2005 , Page(s): 2416 - 2427
    Cited by:  Papers (51)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1240 KB) |  | HTML iconHTML  

    A third-order continuous-time multibit (4 bit) ΔΣ ADC for wireless applications is implemented in a 0.13-μm CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm2. View full abstract»

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  • A low-power multi-bit ΣΔ modulator in 90-nm digital CMOS without DEM

    Publication Year: 2005 , Page(s): 2428 - 2436
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB) |  | HTML iconHTML  

    Multi-bit sigma-delta modulators are widely used in analog-to-digital conversion especially in the modern deep-submicron CMOS process. As the quantizer resolution of ΣΔ modulators increases, the SNR performance improves. However, the feedback DAC has to maintain high linearity. The general practice to achieve that is to use dynamic element matching (DEM). The methodology proposed in this paper will greatly reduce the complexity or even avoid usage of DEM for multi-bit ΣΔ modulators. The proposed methodology-truncation error shaping and cancellation-reduces the feedback DAC levels for multi-bit quantizers. A prototype was designed in a standard CMOS 90-nm process to demonstrate the proposed methodologies. It achieved targeted performance without DEM at low power consumption with small silicon area. View full abstract»

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  • "Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC

    Publication Year: 2005 , Page(s): 2437 - 2445
    Cited by:  Papers (61)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB) |  | HTML iconHTML  

    Self-calibration in approximately 10 000 conversions is demonstrated in a 16-bit, 1-MS/s algorithmic analog-to-digital converter (ADC). Continuous digital background calibration is enabled by introduction of a "split ADC" architecture, in which the die area of a single ADC design is split into two independent converters, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for the background calibration process. Since both ADCs convert the same input, when correctly calibrated their outputs should be equal and the difference should be zero. Any nonzero difference provides information to an error estimation process which adjust calibration parameters in each ADC. For the specific realization of an algorithmic ADC described in this paper, a multiple residue mode amplifier is used to ensure different decision trajectories and provide valid calibration information. The analog sub-system of the ADC is implemented in 0.25-μm CMOS, consumes 105 mW, and has a die size of 1.2 mm × 1.4 mm. View full abstract»

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  • A 50-MS/s (35 mW) to 1-kS/s (15 μW) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation

    Publication Year: 2005 , Page(s): 2446 - 2455
    Cited by:  Papers (28)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (936 KB) |  | HTML iconHTML  

    A novel rapid power-on operational amplifier and a current modulation technique are used in a 10-bit 1.5-bit/stage pipelined ADC in 0.18-μm CMOS to realize power scalability between 1 kS/s (15 μW) and 50 MS/s (35 mW), while maintaining an SNDR of 54-56 dB for all sampling rates. The current modulated power scaling (CMPS) technique is shown to enhance the power scaleable range of current scaling by 50 times, allowing ADC power to be varied by a factor of 2500 while only varying bias currents by a factor of 50. Furthermore, the nominal power is reduced by 20%-30% by completely powering off the rapid power-on opamps during the sampling phase in the pipeline's sample-and-holds. View full abstract»

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  • A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation

    Publication Year: 2005 , Page(s): 2456 - 2468
    Cited by:  Papers (21)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1072 KB) |  | HTML iconHTML  

    A 12-bit 1.6-GS/s digital-to-analog converter (DAC) implemented with 4-μm2 GaAs HBT process is presented. Return-to-zero (RZ) current switches are added to current steering DAC for high-frequency wideband applications to achieve 800-MHz bandwidth at first and second Nyquist band without the need for a reverse sinc equalization filter in wideband transmitter application. The RZ circuit also improves spectral purity by screening the switching noise from the analog output during data transition. Measured performance shows two-tone third-order harmonic distortion of -70 dB at 1.5-GHz output frequency, clocked at 1.6 GHz. Reliable interface with CMOS logic IC is guaranteed with the inclusion of a four-clock-deep FIFO circuit. The DAC dissipates 1.2 W at -5 V when sampled with 1.6-GHz clock, with typical output voltage swing of 1.2 VPP. View full abstract»

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  • All-digital PLL and transmitter for mobile phones

    Publication Year: 2005 , Page(s): 2469 - 2482
    Cited by:  Papers (250)  |  Patents (36)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1432 KB) |  | HTML iconHTML  

    We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5° rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 μs settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm2 and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power. View full abstract»

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  • An 802.11g WLAN SoC

    Publication Year: 2005 , Page(s): 2483 - 2491
    Cited by:  Papers (17)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1296 KB) |  | HTML iconHTML  

    A single-chip IEEE-802.11g-compliant wireless LAN system-on-a-chip (SoC) that implements all RF, analog, digital PHY and MAC functions has been integrated in a 0.18-μm CMOS technology. The IC transmits 0-dBm EVM-compliant output power for a 64-QAM OFDM signal. The overall receiver sensitivities are better than -92 and -73 dBm for data rates of 6 and 54Mb/s, respectively. View full abstract»

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  • A fully integrated SOC for 802.11b in 0.18-μm CMOS

    Publication Year: 2005 , Page(s): 2492 - 2501
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2008 KB) |  | HTML iconHTML  

    A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-μm CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range. View full abstract»

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  • A fully integrated 24-GHz phased-array transmitter in CMOS

    Publication Year: 2005 , Page(s): 2502 - 2514
    Cited by:  Papers (54)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3504 KB) |  | HTML iconHTML  

    This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-μm CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 Ω, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to- ratio of 23 dB with raw beam-steering resolution of 7° for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm × 2.1 mm of die area. View full abstract»

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  • A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity

    Publication Year: 2005 , Page(s): 2515 - 2524
    Cited by:  Papers (47)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1288 KB) |  | HTML iconHTML  

    A fully integrated four-channel multi-antenna receiver intended for beamforming and spatial diversity applications is presented. It can also be used as a low-power area-efficient range extender for spatially multiplexed multi-antenna systems that are poised to become mainstream in the near future. Implemented in a 90-nm CMOS technology, each channel weights its input signal by a complex weight with full 360° phase shift programmability using vector combinations of variable-gain amplifiers, thus obviating the need for expensive phase shifters. The chip consumes 140 mW from a single 1.4-V supply and achieves 12 dB of array gain with all four channels activated and >20 dB direction-of-arrival-dependent interference rejection. View full abstract»

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  • A CMOS TV tuner/demodulator IC with digital image rejection

    Publication Year: 2005 , Page(s): 2525 - 2535
    Cited by:  Papers (24)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1504 KB) |  | HTML iconHTML  

    Superheterodyne TV tuners have been implemented in discrete forms using tunable RF and SAW IF filters. Integrating TV tuners in CMOS technology without them is a challenging task to cope with technical issues such as harmonic mixing and image. The image rejection in low- or zero-IF systems has been limited to 30-40 dB by analog imperfections such as I/Q path gain and phase mismatches. A single-chip low-IF TV tuner solution is proposed so that the image can be suppressed digitally using an image cancellation technique based on a complex one-tap LMS signal decorrelation algorithm. Programmable digital filtering and video/sound demodulation make a multistandard TV tuner feasible in the 48-860 MHz VHF/UHF band. The chip has a maximum gain of 63 dB and an input automatic gain control (AGC) range from -15 to 25 dB with 0.85-dB steps. It achieves an image and IF rejection of 60 dB, a peak carrier-to-noise ratio (CNR) of 55 dB, and a peak sound signal-to-noise ratio (SNR) of 44 dB without frequency modulation (FM) de-emphasis. The prototype occupies 6×6 mm2 in 0.25-μm CMOS and consumes 1 W at 2.5 V. View full abstract»

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  • A direct-conversion receiver for DVB-H

    Publication Year: 2005 , Page(s): 2536 - 2546
    Cited by:  Papers (48)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB) |  | HTML iconHTML  

    A fully integrated low-power ultrahigh-frequency (UHF) tuner integrated circuit (IC) design for the digital video broadcasting-handheld (DVB-H) market is presented. A direct-conversion receiver is chosen over classical digital video broadcasting-terrestrial (DVB-T) architectures. The tuner IC covers UHF bands IV/V. The solution is based on a radio frequency integrated circuit (RFIC) and external low-noise amplifier (LNA) to meet the noise figure (NF) specification of 5 dB, IIP3 of 4dBm, and Gain of 89 dB. The IC includes an LNA, dual quadrature mixers, multiple bandwidth baseband (BB) filtering, three 4X voltage-controlled oscillators (VCOs), integer phase-locked loop (PLL), and reference oscillator. The design is implemented in a SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) technology and the die area is 11.5 mm2. View full abstract»

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  • A 17-mW 0.66-mm2 direct-conversion receiver for 1-Mb/s cable replacement

    Publication Year: 2005 , Page(s): 2547 - 2554
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB) |  | HTML iconHTML  

    A very-low-cost wireless personal area network (WPAN) receiver implemented in 0.25-μm CMOS technology consumes 17mW of power and occupies an area of 0.66 mm2. Simplicity in the physical layer, which still supports the 1-Mb/s requirement, allows for power savings in the receive front-end. A new coding scheme permits the integration of a high-pass filter to mitigate DC offset and 1/f noise. A linear front-end eliminates the external band-preselect filter. This die area is the smallest reported for Bluetooth-class front-ends. View full abstract»

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  • A UWB CMOS transceiver

    Publication Year: 2005 , Page(s): 2555 - 2562
    Cited by:  Papers (100)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (992 KB) |  | HTML iconHTML  

    A direct-conversion ultra-wideband (UWB) transceiver for Mode 1 OFDM applications employs three resonant networks and three phase-locked loops. Using a common-gate input stage, the receiver allows direct sharing of the antenna with the transmitter. Designed in 0.13-μm CMOS technology, the transceiver provides a total gain of 69-73 dB and a noise figure of 6.5-8.4 dB across three bands, and a TX 1-dB compression point of -10 dBm. The circuit consumes 105 mW from a 1.5-V supply. View full abstract»

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  • An interference-robust receiver for ultra-wideband radio in SiGe BiCMOS technology

    Publication Year: 2005 , Page(s): 2563 - 2572
    Cited by:  Papers (59)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1288 KB) |  | HTML iconHTML  

    A 3.1-4.8 GHz ultra-wideband (UWB) receiver front-end for high data rate, short-range communication is presented. The receiver, based on the Multi Band OFDM Alliance (MBOA) standard proposal, consists of a zero-IF receive chain and an ultra-fast frequency-hopping synthesizer. The combination of high-linearity RF circuits, aggressive baseband filtering and low local oscillator spurs from the synthesizer results in an interference-robust receiver, having the ability to co-exist with systems operating in the 2.4-GHz and 5-GHz ISM bands. The packaged device shows an overall noise figure of 4.5 dB and has a measured input IP3 of -6 dBm and input IP2 of +25 dBm. Spurious tones generated by the synthesizer are below -45 dBc and -50 dBc in the 2.4-GHz and 5-GHz ISM bands, respectively. The hopping speed is well below the required 9.5 ns. The complete receive chain has been realized in a 0.25 μm BiCMOS technology and draws 78mA from a 2.5-V supply. View full abstract»

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  • A 3.1- to 8.2-GHz zero-IF receiver and direct frequency synthesizer in 0.18-μm SiGe BiCMOS for mode-2 MB-OFDM UWB communication

    Publication Year: 2005 , Page(s): 2573 - 2582
    Cited by:  Papers (43)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1104 KB) |  | HTML iconHTML  

    A direct conversion receiver for ultra-wideband (UWB) applications operates for 3.1 to 8.2 GHz and gives a noise figure of 3.3 to 4.1 dB and a conversion gain of 52 dB. The chip includes the RF receive chain and a 16-GHz quadrature VCO to generate seven carrier frequencies from 3.4 to 7.9 GHz. The circuit was fabricated in a 0.18-μm SiGe BiCMOS process and consumes 88 mA from a 2.7-V supply. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan