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IEE Proceedings E - Computers and Digital Techniques

Issue 6 • Date Nov 1988

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Displaying Results 1 - 8 of 8
  • ECL fault modelling

    Publication Year: 1988, Page(s):312 - 317
    Cited by:  Papers (11)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (464 KB)

    A procedure for describing an ECL circuit at the gate level is proposed. All voltages and currents which switch during circuit operation are described by logic variables, and thus the 'stuck line' model can be effectively applied to describe circuit failures. Faults resulting from open connections and short circuits between transistor terminals are considered in detail. View full abstract»

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  • Scale based algorithm for recognition of blurred planar objects

    Publication Year: 1988, Page(s):307 - 311
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (432 KB)

    The paper presents an algorithm based on scale-space analysis, for the recognition of blurred planar objects. Apart from satisfying the usual requirements for invariance under translation, rotation and scaling, the algorithm is also invariant under blurring, that is, across all levels of detail or scales. The technique makes use of the spatial coincidence of the inflexion points on the object cont... View full abstract»

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  • Techniques for improving stability rate of linear predictive image coding schemes

    Publication Year: 1988, Page(s):298 - 306
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (724 KB)

    Following the considerable success that linear predictive coding (LPC) has had in speech compression, the technique has been applied to the coding of two-dimensional (2-D) signals such as natural images. Unlike its one-dimensional (1-D) counterpart, the 2-D technique is not guaranteed to be stable. It is found that two much correlation in the signal causes a significant proportion of the analysis ... View full abstract»

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  • Fault tolerance: step towards WSI

    Publication Year: 1988, Page(s):289 - 297
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (896 KB)

    Since the early 1960s, semiconductor chips have matured from single transistor devices to 1 million transistors per chip. This increase in integration has been achieved by reducing transistor dimensions, and by increasing chip sizes. However, physical limits are being reached as submicrometre dimensions are approached. Therefore, there is need for larger chip, and wafer, sizes. Manufacturers use d... View full abstract»

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  • Wafer scale integration

    Publication Year: 1988, Page(s):281 - 288
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (832 KB)

    The history of integrated circuit development has been one of continually decreasing feature size, accompanied by a much more gradual increase in chip dimensions. There are obvious limits to both of these trends. In the case of chip size, clearly, the limit is the whole wafer, offering a circuit area on a 15 cm wafer that is roughly 175 times larger than current VLSI chips. Such a step function in... View full abstract»

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  • Algorithms for multiplication in Galois field for implementation using systolic arrays

    Publication Year: 1988, Page(s):336 - 339
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (372 KB)

    Operations in finite fields find diverse applications. Circuits have been designed for carrying out such operations. In the paper, two circuits that carry out multiplication in GF(2p) have been presented. These circuits are suitable for implementation using VLSI techniques and are simpler than existing circuits. The architecture used is that of systolic arrays and consists of regular in... View full abstract»

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  • Simplified procedure for correcting both errors and erasures of Reed-Solomon code using Euclidean algorithm

    Publication Year: 1988, Page(s):318 - 324
    Cited by:  Papers (15)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (440 KB)

    It is well known that the Euclidean algorithm or its equivalent, continued fractions, can be used to find the error locator polynomial and the error evaluator polynomial in Berlekamp's key equation that is needed to decode a Reed-Solomon (RS) code. In the paper, a simplified procedure is developed and proved to correct erasures as well as errors by replacing the initial condition of the Euclidean ... View full abstract»

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  • Towards effective nonlinear cryptosystem design

    Publication Year: 1988, Page(s):325 - 335
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (756 KB)

    The paper describes the design of nonlinear Boolean functions. The first part reviews the case of Boolean functions of n variables. The second part addresses the problem of the generation of Boolean permutations to obtain the collection of nonlinear Boolean functions. View full abstract»

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