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IEEE Micro

Issue 2 • Date April 1988

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Displaying Results 1 - 6 of 6
  • Realization of Gmicro/200

    Publication Year: 1988, Page(s):12 - 21
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    The Gmicro/200, a microprocessor that has been developed as part of Japan's TRON (The Real-Time Operating Nucleus) project, is described. This microprogram-based processor with six-state pipeline, 730000 transistors and on-chip caches will serve in an engineering workstation or a high-speed graphics accelerator system. The authors discuss features of the instruction set; memory management; handlin... View full abstract»

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  • Implementation of the V60/V70 and its FRM function

    Publication Year: 1988, Page(s):22 - 36
    Cited by:  Papers (6)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1378 KB)

    A description is given of the V60/V70, the first commercially based, general-purpose 32-bit microprocessor in Japan. Its functions include on-chip floating-point operations, a high-level-language-oriented architecture, software debugging support, and support functions to promote a high level of system reliability. Because high reliability is so important, the V60/V70 contains functional redundancy... View full abstract»

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  • The TX1 32-bit microprocessor: performance analysis, and debugging support

    Publication Year: 1988, Page(s):37 - 46
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    The 32-bit TX1 microprocessor, developed to meet the architectural specification of Japan's TRON (The Real-Time-Operating Nucleus) project, has been given a loosely coupled pipeline structure to meet the demands of high-performance systems. The authors discuss the design architecture of the TX1, provide some performance analysis for the design, and describe the debugging feature provided on the pr... View full abstract»

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  • Introducing Tobus: the system bus in the TRON architecture

    Publication Year: 1988, Page(s):47 - 59
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (634 KB)

    The Japanese TRON (The Real-Time Operating Nucleus) project has as its goal the design of a computer architecture that includes a CPU, operating systems and a man-machine interface. Peripherals are portable because TRON designers set a board-level standard for the system bus protocol. The end product transfers data at rates from 50 M to 100 M bytes/s. A description is given of Tobus, the system bu... View full abstract»

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  • Applying the mu BTRON bus to a music LAN

    Publication Year: 1988, Page(s):60 - 66
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (474 KB)

    The BTRON computer architecture, developed as part of the Japanese TRON (The Real-Time Operating Nucleus) project, contains specifications for several buses. The application of one of these, the mu BTRON bus, as a music local area network, is discussed. Simulation results for mu BTRON bus performance when electronic musical instruments are connected to BTRON-based computers are reported. Electroni... View full abstract»

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  • A RISC architecture with two-size, overlapping register windows

    Publication Year: 1988, Page(s):67 - 80
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1108 KB)

    The issues involved in designing multiple-register window schemes are examined, and fixed-size, variable-size and two-size window organizations are discussed. These three multiple-register approaches are compared. A detailed example is presented, showing that the proposed two-size register window scheme has significant advantages over both fixed-size and variable-size schemes. A prototype design i... View full abstract»

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IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

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Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center