IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 1 • Jan 1992

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Displaying Results 1 - 12 of 12
  • Calculation of contact currents in device simulation

    Publication Year: 1992, Page(s):128 - 136
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    The authors present an accurate new method for the calculation of the contact currents in a device simulation program which is applicable to arbitrarily shaped device geometries. The method is based on the evaluation of a volume integral of the calculated current densities over the whole device area with a suitably chosen weight function. Different types of weight functions are discussed and compa... View full abstract»

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  • Test pattern generation using Boolean satisfiability

    Publication Year: 1992, Page(s):4 - 15
    Cited by:  Papers (358)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    The author describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: first, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits, and second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach d... View full abstract»

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  • Geometric compaction on channel routing

    Publication Year: 1992, Page(s):115 - 127
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1388 KB)

    A channel compaction algorithm incorporating via minimization and lateral via shifting is discussed. Bump propagation from the center of vias is the crucial phenomenon preventing compaction results from attaining the lower bound. Via minimization reduces the sources of the bumps, and lateral via shifting splits the critical paths which dominate the height of the channel. The authors adopt a contou... View full abstract»

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  • Layout placement for sliced architecture

    Publication Year: 1992, Page(s):102 - 114
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1232 KB)

    The authors define a new, sliced layout architecture for compilation of arbitrary schematics (netlists) into layout for CMOS technology. This sliced architecture uses over-the-cell routing on the second metal layer. The authors define three different architectures with simple folding, interleaved folding, and unrestricted folding and give algorithms for optimizing the layout area for several varia... View full abstract»

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  • Calculating the effects of linear dependencies in m-sequences used as test stimuli

    Publication Year: 1992, Page(s):83 - 86
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    When pseudorandom patterns generated by a linear feedback shift register (LFSR) are used as test stimuli, there is always a concern about the linear dependencies within the sequence of patterns. It is possible for these linear dependencies to preclude a specific test pattern from being present in the sequence of applied patterns. These dependencies and ways to calculate their effects on a particul... View full abstract»

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  • Board-level boundary scan: regaining observability with an additional IC

    Publication Year: 1992, Page(s):68 - 75
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    Partial implementation of boundary-scan IEEE 1149.1 at the board level has a negative effect on testability issues, economics, and total system functionality. An integrated circuit, which will allow boundary-scan architecture to interface with non-boundary-scan parts was designed to increase observability and detectability electronically. The solution offers an opportunity to fuse old and new sili... View full abstract»

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  • Using an asymmetric error model to study aliasing in signature analysis registers

    Publication Year: 1992, Page(s):16 - 25
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    Recent predictions about the aliasing behavior of linear feedback shift registers used in signature analysis with pseudorandom testing are validated experimentally. It is shown that the independent error model accurately predicts aliasing in these signature registers when test sets are selected at random. In practice, however, a circuit's test set is fixed, and it is shown that adopting a more gen... View full abstract»

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  • Synthesis of robust delay-fault-testable circuits: theory

    Publication Year: 1992, Page(s):87 - 101
    Cited by:  Papers (73)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1492 KB)

    The authors give a comprehensive theoretical framework for the analysis and synthesis of delay-fault-testable combinational logic circuits. For each of the common models of delay-fault testability, robust gate-delay faults and robust path-delay faults, they provide the necessary and sufficient conditions for complete testability under that model for two-level circuits. The authors describe the con... View full abstract»

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  • A test methodology for wafer scale system

    Publication Year: 1992, Page(s):76 - 82
    Cited by:  Papers (8)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    To efficiently access and control on-chip design for test (DFT) circuitry, a standard test interface is required. A uniform testing interface is defined for each functional cell, with built-in self-test incorporated whenever possible. Use of a standard interface will reduce test complexity and costs by allowing entire wafer probing by a common standardized probe card, irrespective of the number of... View full abstract»

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  • The pseudoexhaustive test of sequential circuits

    Publication Year: 1992, Page(s):26 - 33
    Cited by:  Papers (25)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for th... View full abstract»

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  • A hierarchical test pattern generation system based on high-level primitives

    Publication Year: 1992, Page(s):34 - 44
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1100 KB)

    The authors present an extension of the automatic test pattern generation system SOCRATES to a hierarchical test pattern generation system for combinational and scan-based circuits. The proposed system is based on predefined high-level primitives, e.g., multiplexers and adders. The exploitation of high-level primitives leads to significant improvements in implication, unique sensitization, and mul... View full abstract»

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  • A framework and method for hierarchical test generation

    Publication Year: 1992, Page(s):45 - 67
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2152 KB)

    The authors present an algorithm for hierarchical test generation based on module-oriented decision making (MODEM). The algorithm deals with combinational logic modules and the traditional single-stuck-at model. Modules and faults are captured at the function as well as the gate level. The benefits of hierarchy are realized by introducing a generic module representation and the concepts of a dynam... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu