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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 12 • Date Dec. 2005

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  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2005, Page(s): c2
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  • Editorial

    Publication Year: 2005, Page(s):1809 - 1810
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  • Platform-based design from parallel C specifications

    Publication Year: 2005, Page(s):1811 - 1826
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB) | HTML iconHTML

    This paper presents Disydent, a framework dedicated to system-on-a-chip (SoC) platform-based design for shared memory multiple instructions multiple data (MIMD) architectures. We define a platform-based design problem as a triplet (system, application, constraints) where the system is both an operating system (OS) and a hardware (HW) template that can be enhanced with dedicated coprocessors. Our c... View full abstract»

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  • Analysis of energy reduction on dynamic voltage scaling-enabled systems

    Publication Year: 2005, Page(s):1827 - 1837
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB) | HTML iconHTML

    Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency, based on the computation load, to provide the desired performance with the minimal amount of energy consumption. It has been demonstrated as one of the most effective low-power system design techniques, particularly for real-time embedded systems. Most existing work are on two different system models t... View full abstract»

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  • Preserving the film coefficient as a parameter in the compact thermal model for fast electrothermal simulation

    Publication Year: 2005, Page(s):1838 - 1847
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    Compact thermal models are often used during joint electrothermal simulation of microelectromechanical systems (MEMS) and circuits. Formal model reduction allows generation of compact thermal models automatically from high-dimensional finite-element models. Unfortunately, it requires fixing a film coefficient employed to describe the convection boundary conditions. As a result, compact models prod... View full abstract»

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  • An efficient 3-D spectral-element method for Schrödinger equation in nanodevice simulation

    Publication Year: 2005, Page(s):1848 - 1858
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    A three-dimensional (3-D) spectral-element method (SEM) based on Gauss-Lobatto-Legendre (GLL) polynomials is proposed to solve the Schrödinger equation in nanodevice simulation. Galerkin's method is employed to obtain the system equation. The high-order basis functions employed are orthogonal and the numerical quadrature points are the same as the GLL integration points, leading to a diagonal... View full abstract»

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  • Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

    Publication Year: 2005, Page(s):1859 - 1880
    Cited by:  Papers (235)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB) | HTML iconHTML

    In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations. A method to predict the yield of a memory chip based on the cell-failure probability is proposed. A methodology to statistically design the SRAM cell and the memory organization is propose... View full abstract»

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  • Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation

    Publication Year: 2005, Page(s):1881 - 1893
    Cited by:  Papers (43)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB) | HTML iconHTML

    Quantum-dot cellular automata (QCA) offers a new computing paradigm for nanotechnology. The basic logic elements of this technology are the majority voter (MV) and the inverter (INV). However, an experimental evaluation has shown that MV is not efficiently used during technology mapping by existing logic-synthesis tools. In this paper, we propose the design and characterization of a novel complex,... View full abstract»

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  • Modular SOC testing with reduced wrapper count

    Publication Year: 2005, Page(s):1894 - 1908
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB) | HTML iconHTML

    Motivated by the increasing design for test (DFT) area overhead and potential performance degradation caused by wrapping all the embedded cores for modular system-on-a-chip (SOC) testing, this paper proposes a solution for reducing the number of wrapper boundary register (WBR) cells. By utilizing the functional interconnect topology and the WBRs of the surrounding cores to transfer test stimuli an... View full abstract»

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  • On modeling crosstalk faults

    Publication Year: 2005, Page(s):1909 - 1915
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Traditionally, digital testing of integrated semiconductor circuits has focused on manufacturing defects. There is another class of failures that happens due to circuit marginalities. Circuit-marginality failures are on the rise due to shrinking process geometries, diminishing supply voltage, sharper signal-transition rates, and aggressive styles in circuit design. There are many different margina... View full abstract»

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  • Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets

    Publication Year: 2005, Page(s):1915 - 1924
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    This paper studies the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS), and simultaneous buffer insertion/sizing and tapered wire sizing (BISTWS). For BISUWS, we analyze the optimal total power dissipation under the delay constraints as well as the power-delay tradeoff. For BISTWS, we study the problems of minimizing power dissipat... View full abstract»

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  • Longest-path selection for delay test under process variation

    Publication Year: 2005, Page(s):1924 - 1929
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    Under manufacturing process variation, a path through a net is called longest if there exists a process condition under which the path has the maximum delay among all paths through the net. There are often multiple longest paths for each net, due to different process conditions. In addition, a local defect, such as resistive open or a resistive bridge, increases the delay of the affected net. To d... View full abstract»

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  • Platform-based design for an embedded-fingerprint-authentication device

    Publication Year: 2005, Page(s):1929 - 1936
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    Fingerprint authentication, in an embedded and portable context, requires complex signal, network, and security-protocol processing in a resource-constrained implementation. We present a platform-based design approach for this application, based on a hierarchy of virtual machines (VM). The fingerprint authentication is programmed in Java, C, and VHSIC hardware description language, and mapped onto... View full abstract»

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  • An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters

    Publication Year: 2005, Page(s):1936 - 1946
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB) | HTML iconHTML

    Algorithms that minimize the complexity of multiplication in digital filters focus on reducing the number of adders needed to implement the coefficient multipliers. Previous works have not analyzed the complexity of each adder, which is significant in low-complexity implementation. A multiplication algorithm for low-complexity implementation of digital filters with a minimum number of full adders ... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2005, Page(s): 1947
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  • 2006 IEEE International Conference on Multimedia and Expo (ICME)

    Publication Year: 2005, Page(s): 1948
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  • 2005 Index

    Publication Year: 2005, Page(s):1949 - 1968
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu