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Electrical and Computer Engineering, Canadian Journal of

Issue 4 • Date Fall 2005

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Displaying Results 1 - 13 of 13
  • Canadian Journal of Electrical and Computer Engineering

    Page(s): 1 - 4
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    Freely Available from IEEE
  • Table of contents

    Page(s): 5 - 6
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    Freely Available from IEEE
  • Message from the editors

    Page(s): 0_7 - 0_8
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    Freely Available from IEEE
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  • Call for papers

    Page(s): 0_11
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    Freely Available from IEEE
  • Low-loss inductors built on PECVD intrinsic amorphous silicon for RF integrated circuits

    Page(s): 179 - 182
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    The quality factor (Q) of inductors on silicon (Si) is limited by the series resistance of the metal at low frequency and by the substrate resistivity at high frequency. Oxide is generally used to isolate the useful signal of the inductor from the lossy substrate. However, stoichiometric silica (SiO2) is processed at a high temperature, which eliminates the possibility of post-CMOS integration. By contrast, plasma enhanced chemical vapour deposition (PECVD) amorphous Si can be deposited at a low temperature and is easily integrated with most Si-based processes. Intrinsic amorphous hydrogenated silicon (i-a-Si:H) also displays low conductivity. In this work, i-a-Si:H deposited at a low temperature (250¿) is used in a novel approach as the isolation material for planar inductors on Si for RF integrated circuits. An improvementof more than 50% in Q is measured when 1.5 µm i-a-Si:H film is deposited on the Si substrate prior to fabrication of the inductor. This result demonstrates the influence of i-a-Si:H film on the RF performance of an inductor. Intrinsic a-Si:H is shown to be a promising material for the isolation of RF devices on low-resistivity Si. View full abstract»

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  • A 0.18 μm CMOS pipelined encoder for a 5 GS/s 4-bit flash analogue-to-digital converter

    Page(s): 183 - 187
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    A high-speed CMOS encoder intended for a 5 gigasample/second (GS/s) 4-bit flash analogue-to-digital converter (ADC) is presented. To meet the speed and power targets of the ADC, low-swing signalling is used in all the internal sub-blocks of the ADC, including the encoder, which is implemented in current-mode logic (CML). To further enhance the encoders speed, two-stage pipelining is used. Details of the architecture are described. The proposed two-stage pipelined encoder as well as an encoder with no pipelining are designed and simulated in a 0.18 µm CMOS technology, and their performances are compared. Simulation results predict a 40% speed improvement for the pipelined encoder. The encoder circuit consumes 4 mW from a 1.8 V supply while operating at 5 GHz. View full abstract»

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  • Reliability-performance-index probability distribution analysis of bulk electricity systems

    Page(s): 189 - 193
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    System reliability performance is usually based on average customer-interruption indices. The average values are valuable information, but provide only a single customer risk dimension without the underlying probability distributions. The average annual indices give no insight as to how reliability may vary from year to year as a result of the random behaviour of a bulk electric system. Reliability-index probability distributions, therefore, provide additional valuable information and a more complete understanding of composite power system behaviour. A significant advantage when utilizing sequential Monte Carlo simulation in bulk electric system reliability analysis is the ability to provide reliability-index probability distributions in addition to the expected values of their indices. This paper illustrates the development of probability distributions for bulk electric system reliability performance indices using sequential simulation. The results obtained using the developed software show that the system performance-index probability distributions have unique characteristics that are basically dependent on the system topology, operating philosophy and conditions. System conditions such as the peak load level and system reinforcement options have significant impacts on the performance-index probability distribution characteristics. The basic concepts and their application in composite power system reliability evaluation are illustrated by application to a small practical test system. View full abstract»

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  • Moderate loading in bit-rounding algorithms for multicarrier systems

    Page(s): 195 - 199
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    Bit-rounding algorithms are practically attractive for their computational efficiency and suitability for integer-bit loading. However, because of the concave nature of the rate-energy relationship, these algorithms often tend to load bits aggressively, which leads to the performanceconstraint violation. In addition, for BPSK and 8-QAM cases, the anomalous behaviour of the SNR-gap rate function also contributes to the performance constraint violation of the existing bit-rounding algorithms. This paper presents an efficient moderate algorithm for estimating the optimum biasing parameter for round-off operation, using exact SNR values instead of the SNR-gap rate function in order to ensure that both the performance and total power constraints are satisfied while rate optimality is achieved. Simulation results show that the proposed moderate algorithm can maintain the optimum rate and avoid the performance constraint violation of its aggressive counterparts for 75 tested cases. View full abstract»

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  • A distributed arithmetic hardware architecture for real-time hough-transform-based segmentation

    Page(s): 201 - 205
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    Real-time segmentation and tracking of biopsy needles is a very important part of image-guided surgery. Since the needle appears as a straight line in medical images, the Hough transform for straight-line detection is a natural and powerful choice for needle segmentation. However, the transform is computationally expensive and in the standard form is ineffective for real-time segmentation applications. This paper proposes a dedicated hardware architecture for the Hough transform based on distributed arithmetic (DA) principles that results in a real-time implementation. The architecture exploits the inherent parallelism of the Hough transform and reduces the overall computation time. The DA Hough transform architecture has been implemented using the Xilinx field-programmable gate array (FPGA). For a 256x256-bit image, the proposed design takes between 0.1 ms and 1.2 ms to process the Hough transform when the feature points in the image are varied from 2% to 50% of the total image; these values are well within the bounds of real-time operation and thus can facilitate needle segmentation in real time. View full abstract»

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  • A new approach for minimization of binary decision diagrams

    Page(s): 207 - 214
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    This paper proposes a new approach that successfully finds the optimal variable orderings for almost all reduced ordered binary decision diagrams (BDDs) in the LGSynth91 benchmark circuits with up to 500 variables. All previously known approaches can solve only functions with less than 64 variables. The progress of the new approach is attributable to the concept of randomized algorithms, which significantly reduce the influence of the initial variable ordering on the minimization performance. Furthermore, the features of different BDD minimization algorithms can also be measured as a result. The results are gradually refined during the minimization progress, such that valid approximate results can be derived before a time-consuming process terminates. The performance of the proposed approach is illustrated through its application on LGSynth91 benchmark circuits. Experimental results demonstrate that the randomized algorithm is properly incorporated; thus the performance remains consistent for a large set of benchmark circuits. In addition to providing a feasible BDD minimization algorithm, this paper presents statistical results and analyses that could be helpful for related research. View full abstract»

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  • Comparative evaluation of control laws based on pulse-width modulation and on hysteresis: application on a current-injection-based three-phase rectifier

    Page(s): 215 - 223
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    In this paper, two control laws based respectively on hysteresis and pulse-width-modulation techniques are applied on a unity-power-factor current-injection- based three-phase rectifier. A theoretical analysis is carried out in order to evaluate the performance of each technique in terms of the line current ripple and the switching frequency. The control-detuning problem, which contributes mainly to the line current distortion, is also considered. In order to highlight the comparative study, a numerical simulation is carried out. View full abstract»

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  • Development and three-dimensional modelling of a biological-tissue grasper tool equipped with a tactile sensor

    Page(s): 225 - 230
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    New surgical procedures, such as minimally invasive surgeries, separate the surgeons hands from the site of an operation. As a result, the surgeons perception of touch is limited to his/her visual abilities fed back from a video camera located at the end of an endoscope. To compensate for this restriction, this study investigates the design, fabrication, testing, and mathematical modelling of an endoscopic grasper tool in which a polyvinylidene fluoride (PVDF) tactile sensor is incorporated. The entire surface of the grasper jaw is active and can be utilized as a means of detecting the magnitude and application point of the applied force. This is in contrast to array-type tactile sensors, in which the areas located between the adjacent sensing elements are inactive. The sensor assembly consists of three distinct layers. The lower layer is made of Plexiglas, while the upper layer is made from micromachined silicon. PVDF film is placed between the upper and lower layers and forms the middle layer. Three-dimensional finite element modelling is used to analyze the performance of the designed system. Good correspondence is obtained between the experimental data and the modelling predictions. View full abstract»

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Aims & Scope

The role of the Canadian Journal of Electrical and Computer Engineering is to provide scientific and professional activity for its members in Canada, the CJECE complements international journals and will be of particular interest to anyone involved in research and development activities in the field of electrical and computer engineering.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Dr. Shahram Yousefi
Dept. of Electrical and Computer
     Engineering
Queen's University