By Topic

IEE Proceedings E - Computers and Digital Techniques

Issue 5 • Sep 1988

Filter Results

Displaying Results 1 - 5 of 5
  • General waveform shape analyser

    Publication Year: 1988, Page(s):241 - 252
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (732 KB)

    Describes a general waveform shape analyser (Wavenet), and a system that uses the representation that it forms for a particular waveform application (Synnet). Wavenet incorporates ideas from models of low-level vision, including Gestalt grouping and the search for symmetry and structure. The novel design includes a lattice network of nodes combined with an attributed grammar, which hunts for perce... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • TSC-error C/D circuits for SEC/DED product codes

    Publication Year: 1988, Page(s):253 - 258
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (460 KB)

    A new design technique for totally self-checking (TSC) error correcting/detecting (C/D) circuits of single-error correcting double-error detecting (SEC/DED) product codes is described. The structure of these circuits achieves concurrent fault detection and location under normal input conditions. A separate internal fault (IF) indication is provided. This improves the reliability, maintainability a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low cost serial multipliers for high-speed specialised processors

    Publication Year: 1988, Page(s):259 - 265
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (600 KB)

    Presents four new arrays for signed number multiplication and multiplication/addition. In these structures, it is assumed that the factors are expressed in 2's complement while the addend and the result are expressed in redundant notation. Two arrays operate in a serial-parallel way, since one of the factors is input in parallel, while the second factor and the addend (in the case of multiplicatio... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CMOS ternary flip-flops and their applications

    Publication Year: 1988, Page(s):266 - 272
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (488 KB)

    Demonstrates a procedure for designing CMOS ternary circuits based on discussion of threshold comparison, transmission, and union operations. Using some basic CMOS ternary circuits, the authors design CMOS ternary flip-flops (tri-flops) such as ternary latch and various master/slave tri-flops. These tri-flops have two additional binary inverse outputs with a fixed threshold. As examples of sequent... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast bridge for efficient LAN-LAN coupling

    Publication Year: 1988, Page(s):273 - 277
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (484 KB)

    Describes the design of a fast bridge between two Cambridge ring local area networks. The main requirements are high speed, a flexible addressing range and high reliability. The bridge implemented is in day to day use as part of TRICE, the distributed computing system implemented at the Department of Electronics and Computer Science at Southampton University. The performance and reliability obtain... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.