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Computers and Digital Techniques, IEE Proceedings E

Issue 3 • Date May 1988

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Displaying Results 1 - 7 of 7
  • VLSI design for diminished-1 multiplication of integers modulo a Fermat number

    Publication Year: 1988 , Page(s): 161 - 164
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (412 KB)  

    The paper presents two new multiplication algorithms for Fermat number transforms which have improved speed, and in which both the algorithm and the hardware circuitry are simplified. These advantages arise from the properties of the diminished-1 addition, which allow the need to generate a rather complicated initial state to be eliminated. Also, a number represented in the diminished-1 number scheme is always one less than its normal binary value, thus enabling the translation step to be avoided by considering the least significant bit (LSB) of the multiplier as a special case having the value LSB+1. One of the algorithms has already been realised using NMOS VLSI technology. The circuit has been designed hierarchically and uses regular structures and is expandable, which makes it very suitable for VLSI implementation. A logic diagram for realisation of the second algorithm is also given and this it to be implemented using CMOS technology. It is estimated that the time taken to complete modulo F4 multiplication would be 1 mu s. View full abstract»

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  • Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture

    Publication Year: 1988 , Page(s): 165 - 172
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    The paper reports an investigation into the design constraints, trade-offs and implementation issues involved in the design of a large content-addressable memory (CAM) for a VLSI CMOS high-speed associative chip architecture: the single chip array processing element SCAPE associative parallel processor. It includes results from a study into determining the general electrical and physical characteristics of a range of CAM cells; details from a case study of the SCAPE chip that predicts the performance of CAMs within a VLSI-based parallel processing computer system, together with the overall impact the CAM design has on the SCAPE chip performance; the selection and implementation engineering of the most cost-effective CAM design for the SCAPE chip. View full abstract»

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  • XPXM/C: a taxonomy of processor coupling techniques

    Publication Year: 1988 , Page(s): 173 - 180
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (904 KB)  

    A well established but ad hoc set of interconnection structures, used in the classification of shared-memory multiprocessors, is developed into a simple orthogonal taxonomy of processor coupling techniques, 'XPXM', based on the multiplicity of simultaneously-active access paths between processors and memory modules. Channel modules are then introduced and used to define the corresponding 'XPXC' taxonomy describing multiprocessors which do not employ shared memory. Examples of existing multiprocessor designs in each class of the combined taxonomy are presented, yielding a representative overview of the coupling techniques in most common use. View full abstract»

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  • Industrial applications of computer vision since 1982

    Publication Year: 1988 , Page(s): 117 - 136
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2364 KB)  

    During the past six years, the use of computer vision systems for industrial applications has become increasingly widespread. In the paper, the application of vision in this context is surveyed and reviewed, according to the principal current application areas of automated visual inspection and visually guided robotic manipulation. Additionally, recently published research and development work for the identification and location of industrial components is discussed, as this forms the basis for improving the existing highly-constrained application of machine vision. The survey is restricted to the period since 1982 in order to complement existing publications at or around that time. View full abstract»

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  • Timing macromodels for CMOS static set/reset latches and their applications

    Publication Year: 1988 , Page(s): 151 - 160
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    Efficient timing macromodels for CMOS static NAND-type and NOR-type latches are developed, to compute analytically their signal timing under different input state transitions. The timing equations in the macromodels are derived from the effective dominant pole of the linearised large-signal equivalent circuit of a latch under the characteristic-waveform consideration. Through extensive comparisons with SPICE simulations, it is found that the macromodels have a maximum error of 22% for the total propagation delay times of the latches, with different device sizes, capacitive loads, device parameter variations, noncharacteristic-waveform input excitations and input-state transitions. When incorporated with the timing models of CMOS combinational logic gates, the macromodels can also be applied to characterise the signal timing of static sequential integrated circuits. Application examples on two CMOS clocked flip-flops and experimental verifications on a fabricated CMOS master-slave T flip-flop are successfully made to confirm the accuracy and applicability of the developed macromodels. Reasonable accuracy, wide applicable ranges and CPU-time, and memory efficiency have made the macromodels very attractive in many CAD applications. View full abstract»

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  • Processor system for realtime video signal processing

    Publication Year: 1988 , Page(s): 181 - 187
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (744 KB)  

    A 10 ns programmable signal processor system for realtime applications in video signal and image processing has been developed and realised. Up to six instructions can be processed in one operation cycle of 10 ns. The high data throughput is attained by pipeline-structure and parallel circuit design. Several program realisations using this processor system have demonstrated that realtime processing of broadband signals with such different algorithms as edge-extractions, two-dimensional DPCM and moving-pattern generation are possible in a programmable processor. View full abstract»

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  • Superchip architecture for implementing large integrated systems

    Publication Year: 1988 , Page(s): 137 - 150
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1772 KB)  

    The paper introduces an architecture embodied in a large silicon chip, or 'superchip', which can be tailored by the user to a specific system to perform a particular processing task. The methodology of system design using the superchip architecture is presented both at the top level of system organisation and at a lower level of system customisation, through a suite of supporting software. The superchip architecture offers defect/fault tolerant capability and system reconfigurability by incorporating, as a key feature, a crossbar switching network in the system. This crossbar switching network connects together all the available processing elements in the super-chip to achieve the required communication. Defect/fault tolerance is achieved by introducing redundancy through the switching network. The optimal redundancy predicted by yield models employed shows how a dramatic improvement over the yield without redundancy can be achieved. This brings the superchip yield up to an economically acceptable level, while keeping the hardware overhead at a minimum. An example is given to illustrate the design and customisation process for implementing and FFT system in the superchip style. View full abstract»

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