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IEE Proceedings - Computers and Digital Techniques

Issue 5 • Date 9 Sept. 2005

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Displaying Results 1 - 15 of 15
  • Hardware/software co-design for virtual machines

    Publication Year: 2005, Page(s):537 - 548
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (2208 KB)

    Hardware/software co-design and (re)configurable computing with field programmable gate arrays (FPGAs) are used to create a highly efficient implementation of the Java virtual machine (JVM). Guidelines are provided for applying a general hardware/software co-design process to virtual machines, as are algorithms for context switching between the hardware and software partitions. The advantages of u... View full abstract»

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  • Data transfer analysis for a pair of asynchronous communication algorithms

    Publication Year: 2005, Page(s):549 - 560
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (294 KB)

    A common form of asynchronous communication mechanism (ACM) provides a one-way data transfer connection between two concurrent processes in which the writer uses a control algorithm to release data within the mechanism and the reader uses a control algorithm to acquire data within the mechanism, without recourse to arbitration or exclusion which could impede the progress of either the writer or th... View full abstract»

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  • Diminished-1 modulo 2n+1 squarer design

    Publication Year: 2005, Page(s):561 - 566
    Cited by:  Papers (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (150 KB)

    Squarers modulo M are useful design blocks for digital signal processors that internally use a residue number system and for implementing the exponentiators required in cryptographic algorithms. In these applications, some of the most commonly used moduli are those of the form 2n+1. To avoid using (n+1)-bit circuits, the diminished-1 number system can be effectively used in modulo 2... View full abstract»

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  • Fastest classes of linearly independent transforms over GF(3) and their properties

    Publication Year: 2005, Page(s):567 - 576
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (361 KB)

    New fastest linearly independent (LI) transforms over Galois field (3) (GF(3)) and their corresponding polynomial expansions have been introduced. The number of required additions and multiplications in new LI transforms is lower when compared with the ternary Reed-Muller transform, which was previously known as the most efficient transform over GF(3). The paper discusses various properties of the... View full abstract»

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  • Multiple fault detection and diagnosis techniques for lookup table FPGAs

    Publication Year: 2005, Page(s):577 - 584
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (217 KB)

    A novel fault detection and diagnosis technique named the 'ping-pong' type approach for field programmable gate arrays (FPGAs) is proposed in the paper. The authors first derive efficient (k+1) test configurations for a single configurable logic block (CLB) which guarantees 100% fault coverage, where k denotes the number of inputs of a lookup table (LUT). Furthermore, the whole CLB array is divide... View full abstract»

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  • Power-aware branch predictor update

    Publication Year: 2005, Page(s):585 - 595
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (331 KB)

    Designers have invested much effort in developing accurate branch predictors. To maintain accuracy, current processors update the predictor regularly and frequently. Although this aggressive approach helps to achieve high accuracy, for a large number of branches, quite often, updating the branch predictor unit is unnecessary as there is already enough information available to the predictor to pred... View full abstract»

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  • Using hyperprediction to compensate for delayed updates in value predictors

    Publication Year: 2005, Page(s):596 - 608
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (439 KB)

    Value prediction has been proposed as a technique to break true data dependences in order to increase the instruction-level parallelism available in programs. Recent work has pointed out, however, that the delay inherent in updating the value prediction table with the actual correct value can introduce a substantial number of wrong value predictions, which can then decrease the overall processor p... View full abstract»

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  • Scan chain ordering technique for switching activity reduction during scan test

    Publication Year: 2005, Page(s):609 - 617
    Cited by:  Papers (10)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (322 KB)

    Scan testing is expensive in power consumption as each test vector requires a large number of shift operations with a high circuit activity. For a scan cell, the number of transitions caused by a test vector being scanned in depends not only on the transitions in the test vector but also on its position in the scan chain. Depending on the circuit structure, the transitions at some scan cells may c... View full abstract»

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  • FPGA implementation of 1D wave equation for real-time audio synthesis

    Publication Year: 2005, Page(s):619 - 631
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (576 KB)

    The paper addresses the potential benefits of using a field programmable gate array (FPGA) as opposed to a traditional processor for music synthesis. The benefits result from the use of a cellular design, with each cell performing identical operations on its own state and the states of its neighbours. This gives advantages of design simplicity through inherent parallelism. A cellular model which h... View full abstract»

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  • Fast specification test of TDMA power amplifiers using transient current measurements

    Publication Year: 2005, Page(s):632 - 642
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (587 KB)

    A novel test methodology for fast and accurate testing of RF power amplifiers used in wireless communication that employ time division multiplexing is presented. The steep cost of high frequency testers can be largely complemented by the proposed method due to its ease of implementation on low cost testers. TDMA power amplifiers usually have a control voltage to operate the device in various modes... View full abstract»

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  • Communication and task scheduling of application-specific networks-on-chip

    Publication Year: 2005, Page(s):643 - 651
    Cited by:  Papers (24)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (364 KB)

    The objective of the paper is to introduce a novel energy-aware scheduling (EAS) algorithm which statically schedules application-specific communication transactions and computation tasks onto heterogeneous network-on-chip (NoC) architectures. The proposed algorithm automatically assigns the application tasks onto different processing elements and then schedules their execution under real-time con... View full abstract»

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  • Efficient substructure sharing methods for optimising the inner-product operations in Rijndael advanced encryption standard

    Publication Year: 2005, Page(s):653 - 665
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (353 KB)

    The Rijndael advanced encryption standard (AES) contains two paired important transformations, MixColumns (inverse MixColumns) and SubByte (inverse SubBytes), the most crucial operations in the AES encryption /decryption processes. They consist of XOR-based inner production operations in GF(28). In the paper, two substructure sharing methods are proposed to reduce the area cost of imple... View full abstract»

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  • Using an operand file to save energy and to decouple commit resources

    Publication Year: 2005, Page(s):666 - 678
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (571 KB)

    The register file of a modern superscalar processor is a critical component of the processor pipeline that can have a large impact on processor performance. Large register files provide larger windows of speculation to the processor and allow greater levels of instruction-level parallelism. However, the access time and energy consumption of these structures can grow quite large when these structur... View full abstract»

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  • Time and space efficient method for accurate computation of error detection probabilities in VLSI circuits

    Publication Year: 2005, Page(s):679 - 685
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (205 KB)

    The authors propose a novel fault/error model based on a graphical probabilistic framework. They arrive at the logic induced fault encoded directed acrylic graph (LIFE-DAG), which is proven to be a Bayesian network, capturing all spatial dependencies induced by the circuit logic. Bayesian networks are the minimal and exact representation of the joint probability distribution of the underlying prob... View full abstract»

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  • Efficient reverse converters for four-moduli sets { 2n-1, 2n, 2n+1, 2n+1-1} and {2n-1, 2n, 2n+1, 2n-1-1}

    Publication Year: 2005, Page(s):687 - 696
    Cited by:  Papers (18)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (325 KB)

    A new reverse conversion algorithm is presented for the four-moduli set {2n-1,2n,2n+1, 2n+1-1}, for even values of n. The number theoretic properties of the popular three-moduli set {2n-1,2n, 2n+1} have been exploited to realise a VLSI efficient alternative to that reported in the literature. The architecture proposed for... View full abstract»

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