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Computers and Digital Techniques, IEE Proceedings -

Issue 6 • Date 4 Nov. 2005

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Displaying Results 1 - 10 of 10
  • Adder methodology and design using probabilistic multiple carry estimates

    Page(s): 697 - 703
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (138 KB)  

    A novel approach for designing estimated carry adders for use in asynchronous circuits is presented. It demonstrates that by using statistical probability of a carry being in a particular state, a 32-bit adder can be constructed in which for the majority of additions there is an improvement in the speed performance of the adder. This methodology shows that each time an additional carry is introduced for carry prediction there is a 50% gain in speed performance over the previous 32-bit addition. This novel adder methodology significantly reduces the addition time, and through simulation and design it has been shown that the 32-bit ESTC adder using multiple carries can dramatically achieve speed and/or area advantages over existing adder circuits. For example using four carries for prediction, comparisons in terms of delay-area product show performance savings of more than 41% over the carry select adder with ripple adder elements, and more than 26% over both carry lookahead and carry select adders based on carry lookahead elements. View full abstract»

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  • Three-stage compression approach to reduce test data volume and testing time for IP cores in SOCs

    Page(s): 704 - 712
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (174 KB)  

    A three-stage compression technique that reduces test data volume and test application time for scan-based testing of intellectual property (IP) cores in system-on-chip integrated circuits is presented. In the first stage, referred to as width compression, the concept of scan chain compatibilities is combined with a method that exploits the logic dependencies between scan chains. This leads to a gated fanout decompression structure that uses c input channels to drive m scan chains (c≪m). Next, static compaction is used to reduce the number of test patterns, a step referred to as height compression. Finally, dictionary-based compression is used to further reduce test data volume. Structural information about the IP cores is not necessary for fault simulation, dynamic compaction, or test generation. By combining the advantages of the gated fan-out structure and dictionary-based compression, the proposed approach significantly reduces the test data volume and testing time with very little hardware overhead for on-chip decompression. Results are presented for the ISCAS-89 benchmarks and for four industrial circuits. View full abstract»

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  • Test generation for embedded circuits under the transparent-scan approach

    Page(s): 713 - 720
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (139 KB)  

    A new test generation procedure is introduced for scan circuits under an approach called transparent-scan. The new test generation procedure targets a circuit-under-test that is embedded in a larger design (it is also applicable to an interconnection of embedded circuits). Transferring deterministic test data to the primary inputs of an embedded circuit from an external source can be expensive. This problem is alleviated as follows. The test generation procedure starts from a given input sequence Ψ that specifies the values of the original primary inputs of the circuit (the primary inputs before scan was added). In this implementation, Ψ is a random input sequence that can be generated by an on-chip test-pattern generator (e.g. a linear-feedback shift register) driving the original primary inputs of the circuit. The test generation procedure transforms Ψ into a test sequence T for the scan circuit under the transparent-scan approach by adding to Ψ the values of the scan select and scan chain inputs. These inputs are easily controllable from the primary inputs of the design. View full abstract»

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  • RTL power estimation in an HDL-based design flow

    Page(s): 723 - 730
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (171 KB)  

    Power estimation at the register-transfer level (RTL) is usually narrowed down to the problem of building accurate power models for the modules corresponding to RTL operators. It is shown that, when RTL power estimation is integrated into a realistic design flow based on an HDL description, other types of primitives need to be accurately modelled. In particular, a significant part of the RTL functionality is realised by sparse logic elements. The proposed estimation strategy replaces the low-effort synthesis that is typically used for this type of fine-grain primitives with an empirical power model based on parameters that can be extracted from either the internal representation of the design or from RTL simulation data. The model can be made scalable with respect to technology, and provides very good accuracy (13% on average, measured on a set of industrial benchmarks). Using a similar statistical paradigm, accurate (about 20% average error) models for the power consumption of internal wires are also presented. View full abstract»

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  • Enhancing behavioural-level design flows with statistical power estimation capabilities

    Page(s): 731 - 737
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (190 KB)  

    Power estimation of behavioural hardware descriptions is a difficult task, as it entails inferring the hardware architecture on which the behavioural specification will be mapped through synthesis before the synthesis is actually performed. To cope with the uncertainties related to handling behavioural descriptions, the concept of statistical estimation is introduced and how a prototype statistical power estimator has been implemented within a high-level design exploration framework (the AspeCts environment) is presented. The experimental results, obtained on a set of C benchmarks, have shown the feasibility of the proposed approach, both in terms of the accuracy of the power estimates and of the reduction of the execution times. View full abstract»

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  • Reducing power dissipation of register alias tables in high-performance processors

    Page(s): 739 - 746
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (506 KB)  

    Modern microprocessor designs implement register renaming using register alias tables (RATs) which maintain the mapping between architectural and physical registers. Because of the non-trivial power that is dissipated in a disproportionately small area, the power density in the RAT is significantly higher than in some other datapath components. Mechanisms are proposed to reduce the RAT power and the power density by exploiting the fundamental observation that most of the generated register values are used by the instructions in close proximity to the instruction producing a value. The first technique disables the RAT lookup for a source register if that register is a destination of an earlier instruction dispatched in the same cycle. The second technique eliminates some of the remaining RAT read accesses, even if the source register value is produced by an instruction dispatched in an earlier cycle. This is done by buffering a small number of recent register address translations in a set of external latches and satisfying some RAT lookup requests from these latches. The net result of applying both techniques is a 30% reduction in the RAT energy with no performance penalty, little additional complexity and no cycle time degradation. View full abstract»

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  • Leakage current aware high-level estimation for VLSI circuits

    Page(s): 747 - 755
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (201 KB)  

    The ever-growing leakage current of MOSFETs in nanometre technologies is the major concern to high performance and power efficient designs. Dynamic power management via power-gating is effective to reduce leakage power, but it introduces power-up current that affects the circuit reliability. The authors present an in-depth study on high-level modelling of power-up current and leakage current in the context of a full custom design environment. They propose a methodology to estimate the circuit area, maximum power-up current, and minimum and maximum leakage current for any given logic function. Novel estimation metrics are built based on logic synthesis and gate-level analysis using only a small number of typical circuits, but no further logic synthesis and gate-level analysis are needed during the high-level estimation. Compared to time-consuming logic synthesis and gate-level analysis, the average errors for circuits from a leading industrial design project are 23.59% for area, 21.44% for maximum power-up current, 15.65% for maximum leakage current and 6.21% for minimum leakage current. In contrast, estimation based on quick synthesis leads to an 11× area difference in gate count for an 8-bit adder. View full abstract»

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  • Switching activity reduction in embedded systems: a genetic bus encoding approach

    Page(s): 756 - 764
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (161 KB)  

    A new approach based on genetic algorithms to reduce power consumption by communication buses in an embedded system is presented. This approach makes it possible to obtain the truth table of an encoder that minimises switching activity on a bus. This method is static, in the sense that the encoders are generated ad hoc for specific traffic. This is not, however, a limiting hypothesis if the application scenario considered is that of embedded systems. An embedded system, in fact, executes the same application throughout its lifetime and so it is possible to have detailed knowledge of the trace of the patterns transmitted on a bus following execution of a specific application. The approach is compared with the most effective ones already presented in literature, on both multiplexed and separate buses. The results obtained demonstrate the validity of the approach, which on average saves up to 50% of the transitions normally required, in addition to their practical applicability, even in an on-chip environment. View full abstract»

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  • Delay bounds based constraint distribution method

    Page(s): 765 - 770
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (153 KB)  

    Transistor sizing is one of the easiest post-processing transforms used to optimise critical paths to fill timing specifications. Most transistor sizing tools, based on nonlinear mathematical programs present high execution times and do not give an indication of the design space explored by the optimisation step. A fast transistor sizing method to address the problem of delay constraint distribution on a CMOS combinatorial path is defined. This method is based on a closed form model of the propagation delay that incorporates the effect of input slew rates on gate delays. The design space is characterised with a technique that allows the determination of the feasible delay bounds of any combinational paths. Then two different constraint distribution methods are defined that are compared to the equal delay distribution and to an industrial tool based on the Newton-Raphson-like algorithm. Validation is obtained on a 0.25 μm process by comparing the different constraint distribution techniques on various benchmarks. View full abstract»

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