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IEEE Micro

Issue 5 • Date Sept.-Oct. 2005

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Displaying Results 1 - 14 of 14
  • [Front cover]

    Publication Year: 2005, Page(s): c1
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    Freely Available from IEEE
  • Table of contents

    Publication Year: 2005, Page(s):2 - 3
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    Freely Available from IEEE
  • High performance at affordable power

    Publication Year: 2005, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (39 KB) | HTML iconHTML

    Regardless of what chip a team is designing, energy efficiency is probably one of the most important criteria. Achieving high performance at affordable power (and therefore, cost) is the overall system goal across a whole range of products that serve the home, entertainment, scientific, and commercial-enterprise segments of the information technology industry. The selection of articles in this iss... View full abstract»

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  • Guest Editors' Introduction: Energy-Efficient Design

    Publication Year: 2005, Page(s):6 - 9
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB) | HTML iconHTML

    Energy efficiency has been a key design constraint for microprocessor development teams since the late 1990s. The fundamental technological issues that have led to this point are quite well understood at this time by industry and academia. Although active (or dynamic) and passive (or standby) components of the net power equation are of concern, in recent years the latter (leakage) aspect of chip p... View full abstract»

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  • Power-conscious design of the Cell processor's synergistic processor element

    Publication Year: 2005, Page(s):10 - 18
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    The authors describe the low-power design of the synergistic processor element (SPE) of the cell processor developed by Sony, Toshiba and IBM. CMOS static gates implement most of the logic, and dynamic circuits are used in critical areas. Tight coupling of the instruction set architecture, microarchitecture, and physical implementation achieves a compact, power-efficient design. View full abstract»

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  • Computer Society Information

    Publication Year: 2005, Page(s): 19
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  • A real-time software platform for the Cell processor

    Publication Year: 2005, Page(s):20 - 29
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    Scalability, efficiency, and programmability are essential for using the cell processor in consumer electronics. A real-time resource scheduler virtualizes the processor cores and ensures the application of real-time constraints at the system level. These features let the platform control resource usage and help exploit the power management features implemented in the cell processor. View full abstract»

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  • Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor

    Publication Year: 2005, Page(s):30 - 38
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    The synergistic processor element is a new architecture oriented for multimedia and streaming processing. In this architecture, the memory is not a cache but a private or scratch pad memory. Such a memory is simple and needs to be high-frequency and large space in low-power. This design uses an 11 fan-out of four (11FO4), six-cycle, fully pipelined, embedded 256-Kbyte SRAM for this purpose. The de... View full abstract»

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  • Long-term workload phases: duration predictions and applications to DVFS

    Publication Year: 2005, Page(s):39 - 51
    Cited by:  Papers (35)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    Computer systems increasingly rely on adaptive dynamic management of their operations to balance power and performance goals. Such dynamic adjustments rely heavily on the system's ability to observe and predict workload behavior and system responses. The authors characterize the workload behavior of full benchmarks running on server-class systems using hardware performance counters. Based on these... View full abstract»

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  • Formal control techniques for power-performance management

    Publication Year: 2005, Page(s):52 - 62
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    These techniques determine when to speed up a processor to reach performance targets and when to slow it down to save energy. They use dynamic voltage and frequency scaling to balance speed and avoid worst case frequency limitations for both multiple-clock-domain and chip multiprocessors. View full abstract»

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  • Energy awareness and uncertainty in microarchitecture-level design

    Publication Year: 2005, Page(s):64 - 76
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    The authors present microarchitecture-level statistical models for characterizing process and system parameter variability, concentrating on gate length and on-chip temperature variations. To assess the effect of microarchitecture decisions on these variations, and vice versa, they propose a joint performance, power, and variability metric that distinguishes among various design choices. View full abstract»

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  • Update on the antitrust ghost in the standard-setting machine [patents]

    Publication Year: 2005, Page(s):77 - 79
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (93 KB) | HTML iconHTML

    This article presents Richard Stern's Micro Law paper in the May-June 2005 issue of IEEE Micro, by two lawyers involved in presenting Hewlett-Packard's RAND proposal to the IEEE PatCom recently. The paper captured the essence of a long-running obstacle to addressing the anticompetitive patent "hold-up" that undermines the open-standards objectives of standards developing organizations (SDOs). That... View full abstract»

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  • Patents: to file or not to file?

    Publication Year: 2005, Page(s):79 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (90 KB) | HTML iconHTML

    In the previous paper, the author discussed the three criteria for patentability: novelty, usefulness, and nonobviousness and the practical value of obtaining a patent in terms of discoverability - the ease with which infringement can be determined, and in terms of avoidance - the ease with which a potential user of someone's invention could achieve similar results without using that invention. In... View full abstract»

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  • Outsourcing and climbing a value chain

    Publication Year: 2005, Page(s): 84
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (57 KB) | HTML iconHTML

    A value chain is a core concept of manufacturing economics. Yet, business reporters often misuse the concept when discussing global outsourcing in electronic equipment manufacturing. This confusion is, fortunately, correctable with one big insight: There are two distinct strategies for improving a firm's value chain. Once these strategies are clarified, it exposes the problems with today's policy ... View full abstract»

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Aims & Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

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Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center