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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 9 • Sept. 2005

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2005, Page(s): c2
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  • Parallel high-throughput limited search trellis decoder VLSI design

    Publication Year: 2005, Page(s):1013 - 1022
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB) | HTML iconHTML

    Limited search trellis decoding algorithms have great potentials of realizing low power due to their largely reduced computational complexity compared with the widely used Viterbi algorithm. However, because of the lack of operational parallelism and regularity in their original formulations, the limited search decoding algorithms have been traditionally ruled out for applications demanding very h... View full abstract»

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  • Pipelining with common operands for power-efficient linear systems

    Publication Year: 2005, Page(s):1023 - 1034
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (517 KB) | HTML iconHTML

    We propose a systematic pipelining method for a linear system to minimize power and maximize throughput, given a constraint on the number of pipeline stages and a set of resource constraints. Unlike most existing pipelining approaches, our method takes the number of pipeline stages as one of the constraints and considers the pipelining as an aspect of power minimization. Operations are retimed so ... View full abstract»

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  • Circuits and architectures for field programmable gate array with configurable supply voltage

    Publication Year: 2005, Page(s):1035 - 1047
    Cited by:  Papers (13)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (803 KB) | HTML iconHTML

    Field programmable gate arrays (FPGAs) with supply voltage (Vdd) programmability have been proposed recently to reduce FPGA power, where the Vdd-level can be customized for FPGA circuit elements and unused circuit elements can be power-gated. In this paper, we first design novel Vdd-programmable and Vdd-gateable interconnect switches with minimal number of configuration SRAM cells. We then evaluat... View full abstract»

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  • Customizable elliptic curve cryptosystems

    Publication Year: 2005, Page(s):1048 - 1059
    Cited by:  Papers (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB) | HTML iconHTML

    This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2/sup m/), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple m-bit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementa... View full abstract»

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  • Equivalent circuit model of on-wafer CMOS interconnects for RFICs

    Publication Year: 2005, Page(s):1060 - 1071
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1563 KB) | HTML iconHTML

    This paper investigates the properties of the on-wafer interconnects built in a 0.18-/spl mu/m CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed mode... View full abstract»

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  • Switch-factor based loop RLC modeling for efficient timing analysis

    Publication Year: 2005, Page(s):1072 - 1078
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB) | HTML iconHTML

    Timing uncertainty caused by inductive and capacitive coupling is one of the major bottlenecks in timing analysis. In this paper, we propose an effective loop RLC modeling technique to efficiently decouple lines with both inductive and capacitive coupling. We generalize the RLC decoupling problem based on the theory of distributed RLC lines and a switch-factor, which is the voltage ratio between t... View full abstract»

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  • Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time

    Publication Year: 2005, Page(s):1079 - 1086
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (667 KB) | HTML iconHTML

    The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns results in favorable results for sequential fault testing. In this paper, a novel algorithm for the generation of SIC pairs is presented, termed Acc... View full abstract»

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  • Autoscan: a scan design without external scan inputs or outputs

    Publication Year: 2005, Page(s):1087 - 1095
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (495 KB) | HTML iconHTML

    We propose a design-for-testability technique for synchronous sequential circuits called autoscan. Autoscan uses scan chains similar to conventional scan. However, it gives up the external scan inputs and outputs in order to eliminate the test data volume associated with them. Scan operations under autoscan improve the circuit testability by allowing the circuit state to be modified through shifti... View full abstract»

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  • Comments on "A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula"

    Publication Year: 2005, Page(s):1096 - 1098
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (131 KB) | HTML iconHTML

    In this brief, the first- and second-order approximation of the quadruple angle formula (QAF) interpolation methods introduced in the paper by Wang et al. in 2004, are revisited. The limitations of those methods are completely overlooked in the paper. One of the limitations is maximum achievable spurious-free dynamic range (SFDR) of the generated sinusoidal signals, which are significantly overest... View full abstract»

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  • Design of a low power wide-band high resolution programmable frequency divider

    Publication Year: 2005, Page(s):1098 - 1103
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and power consumption as compared with the existing designs. Measurement results show that an all-stage programmable counter implemented with this D flip-flop us... View full abstract»

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  • Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

    Publication Year: 2005, Page(s):1103 - 1107
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of leve... View full abstract»

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  • IEEE order form for reprints

    Publication Year: 2005, Page(s):1108 - 108
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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2005, Page(s): 1109
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  • Quality without compromise [advertisement]

    Publication Year: 2005, Page(s): 1110
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  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006)

    Publication Year: 2005, Page(s):1111 - 1112
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu