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IEEE Transactions on Computers

Issue 12 • Date Dec. 2005

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Displaying Results 1 - 18 of 18
  • [Front cover]

    Publication Year: 2005, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2005, Page(s): c2
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  • New efficient MDS array codes for RAID. Part II. Rabin-like codes for tolerating multiple (≥ 4) disk failures

    Publication Year: 2005, Page(s):1473 - 1483
    Cited by:  Papers (20)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    For pt.1 see ibid., vol.54, no.9, p.1071-1080 (2005). A new class of binary maximum distance separable (MDS) array codes which are based on circular permutation matrices are introduced in this paper. These array codes are used for tolerating multiple (≥ 4) disk failures in redundant arrays of inexpensive disks (RAID) architecture. The size of the information part is m × n, where n is the ... View full abstract»

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  • Energy scalable universal hashing

    Publication Year: 2005, Page(s):1484 - 1495
    Cited by:  Papers (13)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB) | HTML iconHTML

    Message authentication codes (MACs) are valuable tools for ensuring the integrity of messages. MACs may be built around a universal hash function (NH) which was explored in the construction of UMAC. In this paper, we use a variation on NH called WH. WH reaches optimally in the sense that it is universal with half the hash length of NH and it achieves perfect serialization in hardware implementatio... View full abstract»

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  • Instruction replication for reducing delays due to inter-PE communication latency

    Publication Year: 2005, Page(s):1496 - 1507
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1288 KB) | HTML iconHTML

    As feature sizes are becoming smaller, wire delays are becoming very critical. Clustering is a popular decentralization approach to reduce the impact of shrinking technologies on clock speed. In this approach, the centralized instruction window is replaced with multiple smaller windows, called clusters (PEs). The performance of these clustered processors depends on the amount of inter-PE communica... View full abstract»

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  • A carry-free architecture for Montgomery inversion

    Publication Year: 2005, Page(s):1508 - 1519
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (896 KB) | HTML iconHTML

    A new carry-free Montgomery inversion algorithm which is suitable for hardware implementation is presented. The algorithm utilizes a new redundant sign digit (RSD) representation and arithmetic to avoid carry propagation in addition and subtraction, which are the atomic operations in the Montgomery inversion algorithm. The proposed algorithm is described in such a way that its hardware realization... View full abstract»

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  • Optimizing hardware function evaluation

    Publication Year: 2005, Page(s):1520 - 1531
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1784 KB) | HTML iconHTML

    We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy requirements, technology mapping, and optimization metrics, such as area, throughput, and latency. Function evaluation f(x) typically consists of range reduction and the actual evaluation on a small convenient interval suc... View full abstract»

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  • Synchro-tokens: a deterministic GALS methodology for chip-level debug and test

    Publication Year: 2005, Page(s):1532 - 1546
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1792 KB) | HTML iconHTML

    This paper describes a novel deterministic globally-asynchronous locally-synchronous (GALS) methodology called "synchro-tokens". Wrappers around the synchronous blocks keep the system globally asynchronous while ensuring that each transition, although arriving at a nondeterministic time, is sensed by the synchronous block during a deterministic cycle of the local clock. This determinism facilitate... View full abstract»

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  • Replication cache: a small fully associative cache to improve data cache reliability

    Publication Year: 2005, Page(s):1547 - 1555
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB) | HTML iconHTML

    Soft error conscious cache design has become increasingly crucial for reliable computing. The widely used ECC or parity-based integrity checking techniques have only limited capability in error detection and correction, while incurring nontrivial penalty in area or performance. The N modular redundancy (NMR) scheme is too costly for processors with stringent cost constraints. This paper proposes a... View full abstract»

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  • An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors

    Publication Year: 2005, Page(s):1556 - 1571
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2120 KB) | HTML iconHTML

    High-performance, out-of-order execution processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction algorithms. Although memory references generated on the wrong path do not change the architectural state of the processor, they affect the arrangement of data in the memory hierarchy. This paper examines the effec... View full abstract»

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  • The granularity metric for fine-grain real-time scheduling

    Publication Year: 2005, Page(s):1572 - 1583
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB) | HTML iconHTML

    This paper investigates the task scheduling problem for real-time systems that provide rate of progress guarantees on task execution. A parameterized task system model, called the (r, g) task system, is introduced that allows rate of progress requirements to be specified in terms of two simple parameters: an execution rate r and a granularity g. The granularity parameter is a new metric that allow... View full abstract»

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  • Joint reliability of medium access control and radio link protocol in 3G CDMA systems

    Publication Year: 2005, Page(s):1584 - 1597
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1280 KB) | HTML iconHTML

    In this paper, we study the reliability as offered jointly by the medium access control (MAC) and the radio link protocol (RLP) for third generation (3G) code division multiple access (CDMA) standards. The retransmission mechanism supported at the RLP layer has a considerable amount of delay (80-100 ms) associated with it; hence, it may not be able to support applications with strict delay require... View full abstract»

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  • FITS: an integrated ILP-based test scheduling environment

    Publication Year: 2005, Page(s):1598 - 1613
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1757 KB) | HTML iconHTML Multimedia Media

    We present a comprehensive and flexible test scheduling environment, called FITS, for testing core-based system-on-chips. Our environment prevents formation of hot spots during test. It also allows trade-off among test time, test access mechanism, power, and test controller/resource constraints. The basic strategy is to use power profile over application time and structural grids of nonembedded co... View full abstract»

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  • Aliasing probability calculations for arbitrary compaction under independently selected random test vectors

    Publication Year: 2005, Page(s):1614 - 1627
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB) | HTML iconHTML

    This paper discusses a systematic methodology for calculating the exact aliasing probability associated with schemes that use an arbitrary finite-state machine to compact the response of a combinational circuit to a sequence of independently selected, random test input vectors. The proposed approach identifies the strong influence of fault activation probabilities on the probability of aliasing an... View full abstract»

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  • Low complexity bit-parallel multiplier for GF(2m) defined by all-one polynomials using redundant representation

    Publication Year: 2005, Page(s):1628 - 1630
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    This paper presents a new bit-parallel multiplier for the finite field GF(2m) defined by an irreducible all-one polynomial. In order to reduce the complexity of the multiplier, we introduce a redundant representation and use the well-known multiplication method proposed by Karatsuba. The main idea is to combine the redundant representation and the Karatsuba method to design an efficient... View full abstract»

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  • 2005 Annual index

    Publication Year: 2005, Page(s):1631 - 1648
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  • TC Information for authors

    Publication Year: 2005, Page(s): c3
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  • [Back cover]

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org