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IEE Proceedings E - Computers and Digital Techniques

Issue 1 • Date Jan 1988

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Displaying Results 1 - 10 of 10
  • Systolic array for the quotient difference algorithm

    Publication Year: 1988, Page(s):60 - 66
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (384 KB)

    The authors consider the problem of producing all the roots of a polynomial p(x)=a0xn+a1xn-1+. . .+an (where all the roots are distinct) by an iterative systolic array. Two basic arrays are considered, one where the position of the roots remain stationary and another where they are non-stationary. The former scheme requires O(n) basic cells, t... View full abstract»

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  • Exhaustive testing of stuck-open faults in CMOS combinational circuits

    Publication Year: 1988, Page(s):10 - 16
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (644 KB)

    CMOS circuits present some unique testing problems. Certain physical failures are not adequately represented by the traditional stuck-at fault model. Opens in transistors or their connections, a 'stuck-open' fault, can require a sequence of tests. A number of test schemes employing exhaustive or pseudo-exhaustive input sequences have appeared in the literature. The authors examine the applicabilit... View full abstract»

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  • Filtering of network addresses in real time by sequential decoding

    Publication Year: 1988, Page(s):55 - 59
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (480 KB)

    The Fano algorithm for sequential decoding permits the simultaneous comparison of a serial bit pattern, with a large number of reference patterns and is applicable to the identification of addresses in local area networks. Such a requirement arises frequently in the design of bridges (filtered, buffered, repeaters) between networks, operating at the data link layer so as to be transparent to vario... View full abstract»

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  • Image transform coding: a case study involving real time signal processing

    Publication Year: 1988, Page(s):41 - 48
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (732 KB)

    A case study is presented which involves the implementation of the discrete cosine transform; a commonly encountered algorithm in image data compression coding. Two commercially available digital signal processing devices are considered. The use of a more highly integrated component, despite offering the potential for greater processing power, does not necessarily result in the most suitable solut... View full abstract»

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  • Physical faults in MOS circuits and their coverage by different fault models

    Publication Year: 1988, Page(s):1 - 9
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (652 KB)

    MOS VLSI circuits are often tested by using the stuck-at fault model to generate and evaluate test sequences that are intended to distinguish faulty from fault-free circuits. However, MOS circuits exhibit a wide variety of failure modes and there is no guarantee that the model accurately reflects the ways in which they fail. The paper gives many examples of faults taken from faulty NMOS circuits a... View full abstract»

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  • Generators for sequences with near-maximal linear equivalence

    Publication Year: 1988, Page(s):67 - 69
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (324 KB)

    A modification of Rueppel's concept of self-decimating sequences enables the design of binary self-clocked linear feedback shift registers of prime period. These in turn may be used as stages in Gollmann's cascade of clock-controlled registers to produce sequences with linear equivalence and period comparable to an upper bound determined by the total number of storage elements. View full abstract»

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  • Clock-controlled shift registers in binary sequence generators

    Publication Year: 1988, Page(s):17 - 24
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (808 KB)

    Cryptographic binary sequence generators are discussed in which a linear feedback shift register is clock controlled in a pseudorandom manner by another register. Huge values of the linear equivalence are readily achieved. To illustrate the possibilities three types of generator are described: First, the output from a clock-controlled shift register is scrambled by a MacLaren-Marsaglia shuffler. S... View full abstract»

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  • Application of the generalised Hough transform to corner detection

    Publication Year: 1988, Page(s):49 - 54
    Cited by:  Papers (12)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (628 KB)

    A new approach to corner detection is described which is based on the generalised Hough transform. The approach has the advantage that it can be used when objects have curved sides or blunt corners, as frequently happens with food products; in addition, it can be tuned for varying degrees of corner bluntness. The method is inherently sensitive: the author shows how it may be optimised for accuracy... View full abstract»

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  • Systolic array implementation of a decimator and an interpolator

    Publication Year: 1988, Page(s):70 - 72
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (128 KB)

    Two systolic arrays for the VLSI implementation of the decimation and interpolating structures advanced by Valenzuela and Constantinides are presented. Each of the resultant arrays consists of basic cells characterised by nearest neighbour interconnections and high throughput rate. View full abstract»

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  • Traversing the VLSI design hierarchy for a new, fast systolic stack

    Publication Year: 1988, Page(s):25 - 40
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1448 KB)

    The design of a new, fast systolic stack is systematically carried out by traversing the qualitatively distinct levels of representation of the VLSI design hierarchy. Included in the overall VLSI design process is a formal verification of design correctness, circuit design and layout, as well as a performance analysis of area, time, clock frequency and design extendability. The novel systolic netw... View full abstract»

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