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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 11 • Date Nov. 2005

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2005, Page(s): c2
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  • On the optimization of heterogeneous MDDs

    Publication Year: 2005, Page(s):1645 - 1659
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB) | HTML iconHTML

    This paper proposes minimization algorithms for the memory size and the average path length (APL) of heterogeneous multivalued decision diagrams (MDDs). In a heterogeneous MDD, each multivalued variable can take different domains. To represent a binary logic function using a heterogeneous MDD, we partition the binary variables into groups with different numbers of binary variables and treat the gr... View full abstract»

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  • An efficient profile-based algorithm for scratchpad memory partitioning

    Publication Year: 2005, Page(s):1660 - 1676
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1024 KB) | HTML iconHTML

    Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption, and die area. The main challenge in SPM design is to optimally map memory locations to scratchpad locations. This paper describes an algorithm to solve such a mapping problem by means of dynamic programming applied to a synthesizable hardware ... View full abstract»

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  • Input space-adaptive optimization for embedded-software synthesis

    Publication Year: 2005, Page(s):1677 - 1693
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB) | HTML iconHTML

    This paper presents a technique for exploiting input statistics for energy and performance optimization of embedded software. The proposed technique is based on the fact that the computational complexities of programs or subprograms are often highly dependent on the values assumed by input and intermediate program variables during execution. This observation is exploited in the proposed software s... View full abstract»

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  • Generation of distributed logic-memory architectures through high-level synthesis

    Publication Year: 2005, Page(s):1694 - 1711
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1336 KB) | HTML iconHTML

    With the increasing cost of on-chip global communication, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, etc.) throughout the chip, while restricting computations and communications to geographic proximities. In this paper, we present a methodology for high-level synthesis (HLS) of distribu... View full abstract»

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  • Power modeling and characteristics of field programmable gate arrays

    Publication Year: 2005, Page(s):1712 - 1724
    Cited by:  Papers (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB) | HTML iconHTML

    This paper studies power modeling for field programmable gate arrays (FPGAs) and investigates FPGA power characteristics in nanometer technologies. Considering both dynamic and leakage power, a mixed-level power model that combines switch-level models for interconnects and macromodels for look-up tables (LUTs) is developed. Gate-level netlists back-annotated with postlayout capacitances and delays... View full abstract»

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  • Modeling delay and noise in arbitrarily coupled RC trees

    Publication Year: 2005, Page(s):1725 - 1739
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Closed-form equations for second-order transfer functions of general arbitrarily coupled resistance-capacitance (RC) trees with multiple drivers are reported. The models allow precise delay and noise calculations for systems of coupled interconnects with guaranteed stability and represent the minimum complexity associated with this class of circuits. Their accuracy is extensively compared against ... View full abstract»

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  • Divide-and-concatenate: an architecture-level optimization technique for universal hash functions

    Publication Year: 2005, Page(s):1740 - 1747
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    The authors present an architectural optimization technique called divide-and-concatenate for hardware architectures of universal hash functions based on three observations: 1) the area of a multiplier and associated data path decreases quadratically and their speeds increase gradually as their operand size is reduced; 2) multiplication is at the core of universal hash functions and multipliers co... View full abstract»

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  • Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs

    Publication Year: 2005, Page(s):1748 - 1759
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    A resistive-open defect is an imperfect circuit connection that can be modeled as a defect resistor between two circuit nodes that should be connected. A stuck-open (SOP) defect is a complete break (no current flow) between two circuit nodes that should be connected. Conventional single stuck-at fault diagnosis cannot precisely diagnose these two defects because the test results of defective chips... View full abstract»

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  • Nonlinear decision boundaries for testing analog circuits

    Publication Year: 2005, Page(s):1760 - 1773
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB) | HTML iconHTML

    A neural classifier that learns to separate the nominal from the faulty instances of a circuit in a measurement space is developed. Experimental evidence, which demonstrates that the required separation boundaries are, in general, nonlinear, is presented. Unlike previous solutions that build hyperplanes, the proposed classifier is capable of drawing nonlinear hypersurfaces. A new circuit instance ... View full abstract»

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  • Application-independent testing of FPGA interconnects

    Publication Year: 2005, Page(s):1774 - 1783
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB) | HTML iconHTML

    We present a new automatic test-configuration-generation technique for application-independent manufacturing testing of the interconnection network of static-random-access-memory-based field programmable gate arrays (FPGAs). This technique targets detection of open and bridging faults in the wiring channels and programmable switches in the interconnects. Experimental results on Xilinx Virtex FPGAs... View full abstract»

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  • Probability distribution of signal arrival times using Bayesian networks

    Publication Year: 2005, Page(s):1784 - 1794
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB) | HTML iconHTML

    This paper presents a new method based on Bayesian networks (BNs) for computing the exact probability distribution of the delay of a circuit. The method is based on BNs, which allows an efficient means to factor the joint probability distributions over variables in a circuit graph. The space complexity of the method presented here is O(m|C|), where m is the number of distinct values tak... View full abstract»

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  • False coupling exploration in timing analysis

    Publication Year: 2005, Page(s):1795 - 1805
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    As integrated circuit technology continues to scale into the nanometer regime, the effect of crosstalk on circuit timing becomes significant. Static timing analysis shows that crosstalk routinely adds 10% to 20% delay to the critical path of a design. However, many aggressor/victim switching combinations are infeasible due to inherent circuit operating constraints, thereby contributing to the mism... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2005, Page(s): 1806
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  • 2006 IEEE International Conference on Multimedia and Expo (ICME)

    Publication Year: 2005, Page(s): 1807
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  • 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2006)

    Publication Year: 2005, Page(s): 1808
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu