By Topic

Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 10 • Date Oct. 2005

Filter Results

Displaying Results 1 - 25 of 34
  • Table of contents

    Page(s): c1 - c4
    Save to Project icon | Request Permissions | PDF file iconPDF (97 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems–I: Regular Papers publication information

    Page(s): c2
    Save to Project icon | Request Permissions | PDF file iconPDF (36 KB)  
    Freely Available from IEEE
  • An 11b 70-MHz 1.2-mm2 49-mW 0.18-μm CMOS ADC with on-chip current/voltage references

    Page(s): 1989 - 1995
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1192 KB) |  | HTML iconHTML  

    This work proposes an 11b 70-MHz CMOS pipelined analog-digital converter (ADC) as one of core circuit blocks for very high speed digital subscriber line system applications. The proposed ADC for the internal use has the strictly limited number of externally connected I/O pins while the ADC employs on-chip CMOS current/voltage references and a merged-capacitor switching technique to improve ADC performances. The ADC implemented in a 0.18-μm 1P4M CMOS technology shows the maximum signal-to-noise distortion ratio (SNDR) of 60 dB at 70 MSample/s. The ADC maintains the SNDR of 58 dB and the spurious-free dynamic resistance of 68 dB for input frequencies up to the Nyquist rate at 60 MSample/s. The measured differential and integral nonlinearities of the ADC are within ±0.63 and ±1.21 LSB, respectively. The active chip area is 1.2 mm2 and the ADC consumes 49 mW at 70 MSample/s at 1.8 V. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 1.5-V square-root domain second-order filter with on-chip tuning

    Page(s): 1996 - 2006
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB) |  | HTML iconHTML  

    A novel square-root domain (SRD) second order filter with automatic tuning control is described. The tuning system is based on a master-slave configuration, where the master is a SRD current-mode magnitude locked loop. The control circuitry allows tuning of the cut-off frequency as well as the quality factor and gain of the filter. The basic building blocks of the complete system are implemented employing a design strategy based on the inherent nonlinear characteristic of Class-AB linear transconductors. A proper biasing scheme in such transconductors leads to operation with very low supply voltages (as low as VGS+2VDSsat). Simulation and numerical results together with measurements from a fabricated prototype in a 0.8-μm CMOS technology are included in order to validate the design technique proposed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator

    Page(s): 2007 - 2022
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB) |  | HTML iconHTML  

    A digital Class-D amplifier comprises a pulsewidth modulator (PWM) and an output stage. In this paper, we simplify the time-domain expression for the algorithmic PWM linear interpolation (LI) sampling process and analytically derive its double Fourier series expression. By means of our derivation, we show that the nonlinearities of the LI process are very low, especially given its modest computation complexity and low sampling frequency. In particular, the total-harmonic distortion (THD) ≈0.02% and foldback distortion is -98.4 dB (averaged from modulation indexes M=0.1 to 0.9) for the 4-kHz voiceband bandwidth @1-kHz input, 48-kHz sampling. We also describe a simple hardware for realizing the LI process. We propose a frequency doubler (with small overheads) for the pulse generator for the PWM, thereby reducing the counter clock rate by 2, leading to a substantial ∼47% power dissipation reduction for the Class-D amplifier. By means of computer simulations and on the basis of experimental measurements, we verify our double Fourier series derivation and show the attractive attributes of a Class-D amplifier embodying our simplified LI sampling expression and reduced clock rate pulse generator. We show that our Class-D amplifier design is micropower (∼60 μW @1.1 V and 48-kHz sampling rate, and THD ≈0.03%) and is suitable for practical power-critical portable audio devices, including digital hearing aids. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Log-domain wavelet bases

    Page(s): 2023 - 2032
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB) |  | HTML iconHTML  

    A novel procedure to approximate wavelet bases using analog circuitry is presented. First, an approximation is used to calculate the transfer function of the filter, whose impulse response is the required wavelet. Next, for low-power low-voltage applications, we optimize the state-space description of the filter for dynamic range, sensitivity and sparsity requirements. The filter design that follows is based on an orthonormal ladder structure with log-domain integrators as the main building blocks. Simulations demonstrate that it approximates the required wavelet base (i.e., Morlet) in an excellent way. The circuit operates from a 1.2-V supply voltage and a bias current of 1.2 μA. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New low-Voltage fully programmable CMOS triangular/trapezoidal function Generator circuit

    Page(s): 2033 - 2042
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    A versatile low-voltage CMOS circuit with a triangular/trapezoidal transconductance characteristic and independently programmable slope (keeping constant height or constant width), height (keeping constant slope or constant width), and horizontal position is presented. Simulation results using Cadence DFW-II that verify the functionality of the circuit with ±1.5-V supplies are presented. A chip prototype has been fabricated in a 0.5-μm technology and experimentally verified. The circuit can find application in the implementation of high resolution, high speed folding analog-to-digital converters, in piecewise-linear approximation, and in the implementation of membership functions in analog and mixed-signal neuro-fuzzy systems. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Log-domain filtering by simulating the topology of passive prototypes

    Page(s): 2043 - 2054
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB) |  | HTML iconHTML  

    A systematic method for designing log-domain filter structures that simulate the topology of the corresponding passive prototypes is introduced in this paper. This has been achieved by transposing the i-υ characteristic equation of each passive element in the linear domain, to the corresponding one in the log domain. The transposition has been done in such a way that, the current that flows through the terminals of the passive element in the linear domain sustains its value in the corresponding log-domain configuration. In this way the linear operation of the whole filter is preserved. With regard to the voltage at each terminal of the passive prototype, this is logarithmically compressed in order to achieve filtering in the log domain. Following the above considerations, the log-domain equivalents of all passive elements of the prototype filter were derived. Having established the equivalents, the procedure for designing high-order log-domain filters is quite facilitated. The validity of the proposed technique is demonstrated through simulation results for a fifth-order elliptic low-pass filter. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-Voltage digitally controlled fully differential current conveyor

    Page(s): 2055 - 2064
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1040 KB) |  | HTML iconHTML  

    Design and simulation of a digitally controlled CMOS fully differential current conveyor (DCFDCC) is presented. A novel current division network (CDN) is used to provide the digital control of the current gain between terminals X and Z of this DCFDCC. The proposed DCFDCC operates under low supply voltage of ±1.5 V. The realization of the DCFDCC using the new CDN is presented by two approaches. First approach has linearly proportional current gain with the digitally controlled parameter of the CDN, while the second approach exhibits current gain between terminals X and Z greater than, or equal to, one. Applications of the DCFDCC in realizing second order universal active filter and variable gain amplifier are given. PSPICE simulation confirms the performance of the proposed blocks and its applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout

    Page(s): 2065 - 2074
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (968 KB) |  | HTML iconHTML  

    A new time-multiplexed switched-capacitor (TM-SC) equalizer is designed on the basis of the previously reported correlated double-sampling integrator and the crosstalk reduction layout approach, which aims at improving the performance aspects on crosstalk, gain loss, 1/f noise and offset. The equalizer, which operates at a single 3-V supply and has a filter bank with 4TM channels, has been fabricated to confirm the effectiveness of the structure using a standard 0.8-μm CMOS process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology

    Page(s): 2075 - 2089
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1520 KB) |  | HTML iconHTML  

    This paper examines the design and implementation of a fourth-order low-pass delta-sigma modulator using a systematic top-down design methodology. Special effort has been made to reduce the power consumption of the modulator through careful system-level modeling and synthesis of circuit specifications. Tradeoffs between circuit building block specifications, optimization time and computing resources are derived. This system-level modeling was tested through the successful implementation of a switched-capacitor delta-sigma analog-to-digital converter integrated circuit (IC) with an output rate slightly exceeding 2 MS/s, in a 1.8-V 0.18-μm, single-polysilicon six-metal standard CMOS process. When sampled at 50 MHz, experimental results reveal that the IC achieves 77.6-dB dynamic range. The prototype consumes 18.8 mW of power, making it one of the lowest power dissipations in switched-capacitor implementations, and for applications where output rates exceed 2 MS/s. When compared to other state-of-the-art switched-capacitor modulators using a widely adopted figure of merit, the modulator dissipates less power and offers superior overall performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-Voltage CMOS subthreshold log-domain filtering

    Page(s): 2090 - 2100
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB) |  | HTML iconHTML  

    This paper presents both a complete set of very low-voltage basic building blocks and a compact design methodology for log filtering in standard or even digital CMOS technologies. The new proposals are based on an alternative translinear loop principle for the MOSFET operating in its subthreshold region. Three different sets of complete basic building blocks are proposed along with all required auxiliary circuitry and a specific matrix design procedure to obtain stable and compact filter implementations. Also, all-MOS filter implementations following these circuit techniques are studied. Simulated and experimental examples are given at 1-V supply voltage for 1.2and 0.35-μm CMOS technologies. The resulting circuit techniques are suitable to integrate very low-voltage low-power system-on-a-chip audio applications, such as hearing aids, in standard CMOS technologies. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Adaptive methods to preserve power amplifier linearity under antenna mismatch conditions

    Page(s): 2101 - 2108
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1440 KB) |  | HTML iconHTML  

    Under antenna mismatch conditions at high output power, voltage clipping (due to collector voltage saturation) is the main cause of power amplifier linearity degradation. To preserve linearity under mismatch three adaptive methods are presented that make use of the detected minimum collector peak voltage. This detected signal controls either the amplifier output power, load-line, or supply voltage. These concepts are generalized analytically, and calculated results compare well to simulations. Measurements demonstrate am error vector magnitude reduction of 5% and an adjacent channel power ratio improvement of 10 dB at a voltage standing wave ratio of 4 for an EDGE amplifier with adaptively controlled output power. These adaptive methods offer a cost and size effective alternative to the use of an isolator. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and analysis of an adaptive transcutaneous power telemetry for biomedical implants

    Page(s): 2109 - 2117
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1432 KB) |  | HTML iconHTML  

    Inductively coupled coil pair is the most common way of wirelessly transferring power to medical implants. However, the coil displacements and/or loading changes may induce large fluctuations in transmitted power into the implant if no adaptive control is used. In such cases, it is required to transmit excessive power to accommodate all the working conditions, which substantially reduces the power efficiency and imposes potential safety concerns. We have implemented a power transfer system with adaptive control technique to eliminate the power variations due to the loading or coupling coefficient changes. A maximum of 250mW power is transmitted through an optimized coil pair driven by Class-E power amplifier. Load shift keying is implemented to wirelessly transfer data back from the secondary to primary side over the same coil pair, with data rate of 3.3 kbps and packet error rate less than 10-5. A pseudo pulsewidth modulation has been designed to facilitate back data transmission along with forward power transmission. Through this back telemetry the system transmits the information on received power, back from implant to primary side. According to the data received, the system adjusts the supply voltage of the Class-E power amplifier through a digitally controlled dc-dc converter, thus varying the power sent to the implant. The key system parameters are optimized to ensure the stability of the closed-loop system. Measurements show that the system can transmit the 'just-needed' power for a wide range of coil separation and/or loading conditions, with power efficiency doubled when compared to the uncompensated link. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new diagnosis approach for handling tolerance in analog and mixed-signal circuits by using fuzzy math

    Page(s): 2118 - 2127
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    A novel analysis method for analog circuits test and diagnosis is described in this paper. Diagnosis hypotheses are represented and fuzzy math is used to express the diagnosis hypotheses and strategy. Based on it, new equivalent fault model is presented and used for test node selection and design for test. Especially, parametric fault test for linear analog circuits with tolerance analysis is presented using both sensitivity method and fuzzy analysis method. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An analysis of charge-pump phase-locked loops

    Page(s): 2128 - 2138
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB) |  | HTML iconHTML  

    The charge pump phase-locked loops with a digital sequential phase frequency detector are analyzed using linear and nonlinear models. Nonlinear analytical maps are derived. The stability analysis results agree with linear analysis results, with higher order corrections. The effects of the loop delay are also discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Decoupled dynamic ternary content addressable memories

    Page(s): 2139 - 2147
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB) |  | HTML iconHTML  

    The content addressable memory (CAM) is a memory in which data can be accessed on the basis of contents rather than by specifying physical address. In the paper, five novel dynamic ternary CAM cells with decoupled match lines are presented. A ternary CAM cell is capable of storing and matching three values: zero (0), one (1), and don't care (X). The proposed dynamic CAM (DCAM) cells range in the number of transistors from 6 n-type transistors up to 10.5 n- and p-type transistors (one transistor is shared between two cells). The cells are capable of fast match and read operations enhancing the performance of the memory system. Using a 0.25-μm CMOS technology, simulations of the proposed CAM cells were performed to compare their performance. With this technology, the shortest match delay is 89.7 ps for the 7.5 DCAM cell. A complete characterization of the five cells is provided in this paper. These results show that the novel CAM cells outperform existing cells. The compact size and low power dissipation of these ternary CAM cells make them suitable for many applications such as routers, database, and associative cache memories. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Micropower gradient flow acoustic localizer

    Page(s): 2148 - 2157
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1256 KB) |  | HTML iconHTML  

    A micropower mixed-signal system-on-chip for three-dimensional localization of a broad-band acoustic source is presented. Direction cosines of the source are obtained by relating spatial and temporal differentials in the acoustic traveling wave field acquired across four coplanar microphones at subwavelength spacing. Correlated double sampling and least-squares adaptive cancellation of common-mode leakthrough in the switched-capacitor analog differentials boost localization accuracy at very low aperture. A second stage of mixed-signal least-squares adaptation directly produces digital estimates of the direction cosines. The 3mm × 3mm chip in 0.5-μm CMOS technology quantizes signal delays with 250-ns resolution at 16-kHz sampling rate, and dissipates 54 μW power from a 3-V supply. Field tests of the processor with acoustic enclosure demonstrated its utility and endurance in tracking ground and airborne vehicles. Applications include acoustic surveillance, interactive multimedia, and intelligent hearing aids. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Open-loop power-stage transfer functions relevant to current-mode control of boost PWM converter operating in CCM

    Page(s): 2158 - 2164
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB) |  | HTML iconHTML  

    This paper presents the analysis of open-loop power-stage dynamics relevant to current-mode control for a boost pulsewidth-modulated (PWM) dc-dc converter operating in continuous-conduction mode (CCM). The transfer functions from input voltage to inductor current, from duty cycle to inductor current, and from output current to inductor current are derived. The delay from the MOSFET gate drive to the duty cycle is modeled using a first-order Pade´ approximation. The derivations are performed using an averaged linear small-signal circuit model of the boost converter for CCM. The transfer functions can be used in modeling the complete boost PWM converter when current-mode control is used. The theory was in excellent agreement with the experimental results, enforcing the validity of the transfer functions derived. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An adaptive maximally decimated channelized UWB receiver with cyclic prefix

    Page(s): 2165 - 2172
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB) |  | HTML iconHTML  

    The frequency channelized receiver based on hybrid filter bank is a promising receiver structure for ultra-wideband (UWB) radio because of its relaxed circuit requirements and robustness to interference. The uncertainties in the analog analysis filters and the time varying nature of the propagation channels necessitate adaptive methods in practical frequency channelized receivers. Adaptive synthesis filters, however, suffer from slow convergence speed especially when maximally decimated to reduce the analog-digital converter sampling frequency. To improve the convergence speed, the cyclic prefix is applied to the transmitted data. The propagation channel and the channelizer can then be modeled as a circulant matrix and block CM, respectively. Such matrix representation enables the transmitted data to be recovered by two cascaded one-tap equalizers, one of which corresponds to the channelizer and the other to the propagation channel. The cascaded structure is attractive as it allows the estimation of the propagation channel and the channelizer, which vary at vastly different rates, to be updated separately. Adaptive algorithms for both the fractionally spaced equalizer and the symbol spaced equalizer are derived. After initial convergence during startup, the adaptive performance of the channelized receiver to different propagation channels is similar to that of an ideal full band receiver. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Passivity verification in delay-based macromodels of electrical interconnects

    Page(s): 2173 - 2187
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB) |  | HTML iconHTML  

    This paper presents a new theory that addresses the issue of passivity in macromodels of electrical interconnects constructed based on the method of characteristics (MoC). The proposed approach develops a new algebraic test to check for passivity in macromodels generated using MoC. The theory behind the developed test is based on deriving the necessary and sufficient conditions for the loss of positive-realness in the admittance matrix of the developed macromodel. An algorithmic procedure is proposed to verify passivity of general macromodels derived from the MoC. The results presented in this paper can be employed to test for positive-realness in dynamical systems described by algebraic delay-differential equations with discrete commensurate delays. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Convolutive blind source separation by minimizing mutual information between segments of signals

    Page(s): 2188 - 2196
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB) |  | HTML iconHTML  

    A method to perform convolutive blind source separation of super-Gaussian sources by minimizing the mutual information between segments of output signals is presented. The proposed approach is essentially an implementation of an idea previously proposed by Pham. The formulation of mutual information in the proposed criterion makes use of a nonparametric estimator of Renyi's α-entropy, which becomes Shannon's entropy in the limit as α approaches 1. Since α can be any number greater than 0, this produces a family of criteria having an infinite number of members. Interestingly, it appears that Shannon's entropy cannot be used for convolutive source separation with this type of estimator. In fact, only one value of α appears to be appropriate, namely α=2, which corresponds to Renyi's quadratic entropy. Four experiments are included to show the efficacy of the proposed criterion. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Linear-phase FIR interpolation, decimation, and mth-band filters utilizing the farrow structure

    Page(s): 2197 - 2207
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    This paper introduces novel linear-phase finite-impulse response (FIR) interpolation, decimation, and Mth-band filters utilizing the Farrow structure. In these new overall filters, each polyphase component (except for one term) is realized using the Farrow structure with a distinct fractional delay. The corresponding interpolation/decimation structures can therefore be implemented using only one set of linear-phase FIR subfilters and one set of multipliers that correspond to the distinct fractional delays. The main advantage of the proposed structures is that they are flexible as to the conversion factors, and this also for an arbitrary set of integer factors, including prime numbers. In particular, they can simultaneously implement several converters at a low cost. The proposed filters can be used to generate both general filters and Mth-band filters for interpolation and decimation by the integer factor M. (In this paper, a general filter for interpolation and decimation by M means a filter having a bandwidth of approximately π/M without the restriction that π/M be included in the transition band. This is in contrast to an Mth-band filter whose transition band does include π/M.) In both cases, the overall filter design problem can be posed as a convex problem, the solution of which is globally optimum. Design examples are included in the paper illustrating the properties and potentials of the proposed filters. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-performance Viterbi decoder with circularly connected 2-D CNN unilateral cell array

    Page(s): 2208 - 2218
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1984 KB) |  | HTML iconHTML  

    A very-high-performance Viterbi decoder with a circularly connected two-dimensional analog cellular neural network (CNN) cell array is disclosed. In the proposed Viterbi decoder, the CNN cells with nonlinear unilateral connections are implemented with electronic circuits at nodes on a trellis diagram. The circuits are circularly connected, forming a cylindrical shape so that the cells of the last stage are connected to those of the first stage. Unilateral connections guide the information to flow circularly around the cylindrical surface. Such configuration enables the conceptually infinite length of the trellis diagram to be reduced to a circuit of limited size. The analog circuits does not require any analog-digital converters, which is the major cause of high power consumption and the quantization error. With the parallel analog processing structure, its decoding speed becomes very high. Also, the decoding mechanism using triggering wave of the CNN circuit does not require the path memory. Circuits for the proposed structure have been designed with HSPICE. Features of the proposed Viterbi decoder are compared with those of the conventional digital Viterbi decoder. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A ZVS PWM inverter with active voltage clamping using the reverse recovery energy of the diodes

    Page(s): 2219 - 2226
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB) |  | HTML iconHTML  

    This paper presents a zero-voltage-switching (ZVS) pulsewidth modulated inverter with active voltage clamping using only a single auxiliary switch. The structure is particularly simple and robust. It is very attractive for single-phase high-power applications. Switching losses are reduced due to implementation of the simple active snubber circuit that provides ZVS conditions for all switches, including the auxiliary one. Its main features are: simple modulation strategy, robustness, low weight and volume, low harmonic distortion of the output current and high efficiency. The principle of operation for steady-state conditions, mathematical analysis and experimental results from a laboratory prototype are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras