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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 8 • Aug. 2005

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2005, Page(s): c2
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  • MOS current mode circuits: analysis, design, and variability

    Publication Year: 2005, Page(s):885 - 898
    Cited by:  Papers (53)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (726 KB) | HTML iconHTML

    The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to... View full abstract»

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  • Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)

    Publication Year: 2005, Page(s):899 - 910
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (805 KB) | HTML iconHTML

    In modern-day VLSI systems, performance and manufacturing costs are being driven by the on-chip wiring needs due to the continuous increase in the number of transistors. This paper proposes a low overhead wave-pipelined multiplexed (WPM) routing technique that harnesses the inherent intraclock period interconnect idleness to implement wire sharing throughout the various hierarchical levels of desi... View full abstract»

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  • A hardware Gaussian noise generator using the Wallace method

    Publication Year: 2005, Page(s):911 - 920
    Cited by:  Papers (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (539 KB) | HTML iconHTML

    We describe a hardware Gaussian noise generator based on the Wallace method used for a hardware simulation system. Our noise generator accurately models a true Gaussian probability density function even at high /spl sigma/ values. We evaluate its properties using: 1) several different statistical tests, including the chi-square test and the Anderson-Darling test and 2) an application for decoding ... View full abstract»

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  • Area-efficient high-throughput MAP decoder architectures

    Publication Year: 2005, Page(s):921 - 933
    Cited by:  Papers (26)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1290 KB) | HTML iconHTML

    Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is recursive and complex, which makes high-speed implementations extremely difficult to realize. In th... View full abstract»

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  • Power-driven simultaneous resource binding and floorplanning: a probabilistic approach

    Publication Year: 2005, Page(s):934 - 942
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB) | HTML iconHTML

    Floorplanning information is integrated during resource binding for better modeling of the interconnect effects on timing and power. Although this integration improves the estimation of the interconnect effects, nonavailability of exact net-lengths can result in suboptimal solutions, because global routing is not yet performed. In this work we propose a probabilistic approach to integrate floorpla... View full abstract»

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  • A fuzzy model for path delay fault detection

    Publication Year: 2005, Page(s):943 - 956
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB) | HTML iconHTML

    A fuzzy model is proposed to analyze the effectiveness of test pairs targeting path delay faults. This model is accurate enough to rank nonrobust tests by accounting for conditions not considered in existing models. It remains fully consistent with the traditional test robustness analysis. Finally, it also provides a coverage metric to be used to rank whole test sets. The proposed model has been i... View full abstract»

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  • BDD decomposition for delay oriented pass transistor logic synthesis

    Publication Year: 2005, Page(s):957 - 970
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB) | HTML iconHTML

    We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and then applying the max-flow min-cut technique to bipartition the BDD optimally under a cost function that measures the delay and area of the decomposed i... View full abstract»

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  • Exponentially tapered H-tree clock distribution networks

    Publication Year: 2005, Page(s):971 - 975
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated for an example clock network by up to 15% while preserving the signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasing ... View full abstract»

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  • Efficient reconfigurable techniques for VLSI arrays with 6-port switches

    Publication Year: 2005, Page(s):976 - 979
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB) | HTML iconHTML

    This paper proposes an efficient techniques to reconfigure a two-dimensional degradable very large scale integration/wafer scale integration (VLSI/WSI) array under the row and column routing constraints, which has been shown to be NP-complete. The proposed VLSI/WSI array consists of identical processing elements such as processors or memory cells embedded in a 6-port switch lattice in the form of ... View full abstract»

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  • Design and analysis of compact dictionaries for diagnosis in scan-BIST

    Publication Year: 2005, Page(s):979 - 984
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (273 KB) | HTML iconHTML

    We present a new technique for generating compact dictionaries for cause-effect diagnosis in scan-BIST. This approach relies on the use of three compact dictionaries and target both modeled and unmodeled faults. We present analytical results that provide useful guidelines for the design of these compact dictionaries. We also present experimental results for the larger ISCAS-89 benchmark circuits f... View full abstract»

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  • Design-for-testability for embedded delay-locked loops

    Publication Year: 2005, Page(s):984 - 988
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (209 KB) | HTML iconHTML

    This paper introduces a new approach to testing a basic analog-only delay-locked loop (DLL) that is embedded in a field-programmable gate array, an application specific integrated circuit, or a system-on-chip (SoC). Part of the DLL circuitry is duplicated and then connected to the DLL in a way that produces a replica of the control voltage. This shadow of the control voltage is used to measure the... View full abstract»

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  • InvMixColumn decomposition and multilevel resource sharing in AES implementations

    Publication Year: 2005, Page(s):989 - 992
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (185 KB) | HTML iconHTML

    Hardware implementations of cryptography face increasingly more stringent demands for lower cost and greater computational power. In order to meet those demands, more efficient approaches to implementations are needed. This paper presents detailed studies of MixColumn and InvMixColumn operations used in Advanced Encryption Standard that aim at their hardware implementations in constrained environm... View full abstract»

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  • A 32-bit carry lookahead adder using dual-path all-N logic

    Publication Year: 2005, Page(s):992 - 996
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (777 KB) | HTML iconHTML

    We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz fo... View full abstract»

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  • Function-based compact test pattern generation for path delay faults

    Publication Year: 2005, Page(s):996 - 1001
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (231 KB) | HTML iconHTML

    We present a function-based nonenumerative automatic test pattern generation (ATPG) methodology for detecting path delay faults (PDFs). The proposed technique consists of a number of topological circuit traversals during each a linear number of Boolean functions is generated per circuit line. From each such function we derive a test that detects many PDFs. The two major strengths of the approach, ... View full abstract»

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  • A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*

    Publication Year: 2005, Page(s):1002 - 1012
    Cited by:  Papers (21)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1745 KB) | HTML iconHTML

    Watermarking is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can either be visible or invisible. A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a viewer on a careful inspect... View full abstract»

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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu