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IEEE Design & Test of Computers

Issue 5 • Date Sept.-Oct. 2005

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Displaying Results 1 - 21 of 21
  • [Front cover]

    Publication Year: 2005, Page(s): c1
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  • On-chip networks

    Publication Year: 2005, Page(s): 393
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    As SoCs continue down the path to smaller geometries and higher integration, their performance measures are changing dramatically. The larger the chip, the greater the disparity between local logic speeds and their interconnect latencies. This issue explores on-silicon integration, discussing challenges in networks on chips, various NoC architectures, the Æthereal NoC, error recovery schemes ... View full abstract»

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  • Table of contents

    Publication Year: 2005, Page(s):394 - 395
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  • Masthead

    Publication Year: 2005, Page(s): 396
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  • Wireless, ESL, DFM, and Power on Stage at 42nd DAC

    Publication Year: 2005, Page(s):397 - 398
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (59 KB) | HTML iconHTML

    The 42nd Design Automation Conference, the world's leading conference and exhibition for design automation, took place in Anaheim, California, from 13 to 17 June 2005. This year's DAC featured a special industry theme day, "Wireless Wednesday," and two keynote talks, by Bernard Meyerson of IBM and Ron Rohrer of Cadence. The technical program explored front-end design issues at the electronic syste... View full abstract»

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  • Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research

    Publication Year: 2005, Page(s):399 - 403
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    The network-on-chip paradigm is an emerging paradigm that effectively addresses and presumably can overcome the many on-chip interconnection and communication challenges that already exist in today's chips or will likely occur in future chips. Effective on-chip implementation of network-based interconnect paradigms requires developing and deploying a whole new set of infrastructure IPs and support... View full abstract»

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  • Design, synthesis, and test of networks on chips

    Publication Year: 2005, Page(s):404 - 413
    Cited by:  Papers (75)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future. View full abstract»

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  • AEthereal network on chip: concepts, architectures, and implementations

    Publication Year: 2005, Page(s):414 - 421
    Cited by:  Papers (338)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    The continuous advances in semiconductor technology enable the integration of increasing numbers of IP blocks in a single SoC. Interconnect infrastructures, such as buses, switches, and networks on chips (NoCs), combine the IPs into a working SoC. Moreover, the industry expects platform-based SoC design to evolve to communication-centric design, with NoCs as a central enabling technology. In this ... View full abstract»

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  • Analysis and implementation of practical, cost-effective networks on chips

    Publication Year: 2005, Page(s):422 - 433
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB) | HTML iconHTML

    This article describes design issues in three NoCs (network on chip) that exploit star and mesh networks, with the objective of comparing area and energy costs. We present new solutions based on mesochronous communication and burst packet transactions. View full abstract»

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  • Analysis of error recovery schemes for networks on chips

    Publication Year: 2005, Page(s):434 - 442
    Cited by:  Papers (138)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms. View full abstract»

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  • Dynamic interconnection of reconfigurable modules on reconfigurable devices

    Publication Year: 2005, Page(s):443 - 451
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB) | HTML iconHTML

    This article presents two approaches to solving the problem of communication between components dynamically placed at runtime on a reconfigurable device. The first is a circuit-routing approach designed for existing FPGAs. This approach uses the reconfigurable multiple bus (RMB). The second, network-based approach targets devices with unlimited reconfiguration capability such as coarse-grained rec... View full abstract»

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  • A reconfigurable manager for dynamically reconfigurable hardware

    Publication Year: 2005, Page(s):452 - 460
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB) | HTML iconHTML

    Dynamic reconfiguration has been a technology solution in search of the right problem to solve. Effective use of the technology requires new programming and task management models. This article describes an approach to dynamic reconfiguration that reduces reconfiguration latency to the point where dynamic multimedia applications can now exploit such platforms. View full abstract»

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  • IEEE Computer Society Information

    Publication Year: 2005, Page(s): 461
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  • Tangram: virtual integration of IP components in a distributed cosimulation environment

    Publication Year: 2005, Page(s):462 - 471
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    IP reuse is essential in embedded SoC design, but IP components can use different modeling languages and present heterogeneous interfaces. To efficiently integrate these heterogeneous components, the Tangram environment supports the remote evaluation of IP components, implementing the virtual integration of these components into distributed cosimulation models. View full abstract»

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  • Inventions: A Result of Risk-Taking, Diversity, and Holistic Thinking—An interview with Bernard S. Meyerson, IBM Fellow, Vice President, and Chief Technologist of IBM's System Technology Group

    Publication Year: 2005, Page(s):472 - 477
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    Yervant Zorian, vice president and chief scientist of Virage Logic and vice president of the IEEE Computer Society, recently interviewed IBM's Bernard S. Meyerson for IEEE Design & Test. Meyerson, a materials science pioneer, has made significant advancements in semiconductor research, notably silicon-germanium heterojunction bipolar transistor technology. He is an IBM Fellow and, in 2002, was... View full abstract»

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  • Verification by the pound

    Publication Year: 2005, Page(s):478 - 479
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  • Conference Reports

    Publication Year: 2005, Page(s):480 - 481
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (94 KB) | HTML iconHTML

    The 10th European Test Symposium (ETS 05) took place in Tallinn, Estonia. This year, the number of Eastern European participants was the highest in symposium history. Full-day tutorials included one on digital test given by Yervant Zorian (Virage Logic, US) and one on analog test given by J. Huertas (IMSE-CNM, Spain). The technical program also featured three plenary keynote addresses, interactive... View full abstract»

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  • Panel Summaries

    Publication Year: 2005, Page(s):482 - 483
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    "IEEE 1500: Embedded core-based test standard—Why should I adopt it?" The IEEE standards committee has now developed a new standard, IEEE 1500, which defines an isolation mechanism for IPs (cores) whereby an IEEE 1500 wrapper can isolate cores for test and debug on a SoC. A panel session at the 23rd IEEE VLSI Test Symposium debated how and why the industry should adopt this new standard. The ... View full abstract»

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  • An update on IEEE P1647: the e system verification language

    Publication Year: 2005, Page(s):484 - 486
    Cited by:  Patents (1)
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    The e language forms the basis of an extensive set of tools and methodologies, collectively known as verification process automation, and almost all major electronics companies worldwide use it. This paper discusses IEEE design automation standards project and shows that how the value of technology can be enhanced by the standardization process. View full abstract»

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  • DATC Newsletter

    Publication Year: 2005, Page(s): 487
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (38 KB) | HTML iconHTML

    In SoC design, the design automation industry is relying too heavily on sustaining technology (small innovations that improve existing products and devices).Disruptive technologies (innovations that radically change our way of doing things) are what cause major jumps in productivity and return for customers. However, disruptive technologies are the least likely to emerge in large companies and, th... View full abstract»

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  • An approach that will NoC your SoCs off!

    Publication Year: 2005, Page(s): 488
    Cited by:  Papers (1)
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    New structured communication fabrics, called networks on chips (NoCs), have emerged for use in SoC designs. The basic concept is to communicate across the chip in the same way that messages are transmitted over the internet today. That is, put a packet-switching network on the chip and send messages back and forth between blocks. Designers have already resolved most of the issues in the Internet d... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty