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Design & Test of Computers, IEEE

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Design & Test of Computers, IEEE

Issue 5 • Date Sept.-Oct. 2005

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Title History

[Front cover]

On-chip networks

Table of contents

Masthead

Wireless, ESL, DFM, and Power on Stage at 42nd DAC

Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research

Design, synthesis, and test of networks on chips

AEthereal network on chip: concepts, architectures, and implementations

Analysis and implementation of practical, cost-effective networks on chips

Analysis of error recovery schemes for networks on chips

Dynamic interconnection of reconfigurable modules on reconfigurable devices

A reconfigurable manager for dynamically reconfigurable hardware

IEEE Computer Society Information

Tangram: virtual integration of IP components in a distributed cosimulation environment

Inventions: A Result of Risk-Taking, Diversity, and Holistic Thinking—An interview with Bernard S. Meyerson, IBM Fellow, Vice President, and Chief Technologist of IBM's System Technology Group

Verification by the pound

Conference Reports

Panel Summaries

An update on IEEE P1647: the e system verification language

DATC Newsletter

An approach that will NoC your SoCs off!

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