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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct. 2005

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Displaying Results 1 - 25 of 42
  • Table of contents

    Page(s): c1 - c4
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  • IEEE Transactions on Electron Devices publication information

    Page(s): c2
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  • Influence of the dynamic access resistance in the gm and fT linearity of AlGaN/GaN HEMTs

    Page(s): 2117 - 2123
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    The decrease of transconductance gm and current gain cutoff frequency fT at high drain current levels in AlGaN/GaN high-electron mobility transistors (HEMTs) severely limits the linearity and power performance of these devices at high frequencies. In this paper, the increase of the differential source access resistance rs, with drain current is shown to play an important role in the fall of gm and fT. The increase of rs occurs due to the quasi-saturation of the electron velocity in the source region of the channel at electric fields higher than 10 kV/cm. This has been confirmed by both experimental measurements and two-dimensional drift-diffusion simulations. Through simulations, we have identified HEMT structures with source implanted regions (or n++ cap layers) as good candidates in order to increase the linearity of the gm and fT versus current profile. View full abstract»

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  • Recessed-gate AlGaN/GaN HFETs with lattice-matched InAlGaN quaternary alloy capping layers

    Page(s): 2124 - 2128
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    In this paper, we present recessed AlGaN/GaN heterojunction field-effect transistors (HFETs) with lattice-matched InAlGaN capping layers, which reduce both ohmic contact resistance and series resistance between the AlGaN and the capping layer. The lattice-matched alloy epitaxial layer with both In and Al high compositions are successfully grown by metal-organic chemical vapor deposition. The grown lattice-matched In0.09Al0.32Ga0.59N capping layer has close total polarization and bandgap to those of the underlying Al0.26Ga0.74N layer. The balanced polarization eliminates the depletion of electrons at the In0.09Al0.32Ga0.59N/Al0.26Ga0.74N interface, which can reduce the series resistance across it. It is also noted that the fabricated HFET exhibits very low ohmic contact resistance of 1.0×10-6 Ω·cm2 or less. Detailed analysis of the source resistance reveals that the series resistance at the In0.09Al0.32Ga0.59N/Al0.26Ga0.74N interface is one fifth as low as the resistance at the conventional GaN/Al0.26Ga0.74N interface. View full abstract»

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  • RF performance and modeling of Si/SiGe resonant interband tunneling diodes

    Page(s): 2129 - 2135
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    The RF performance of two different Si-based resonant interband tunneling diodes (RITD) grown by low-temperature molecular beam epitaxy (LT-MBE) were studied. An RITD with an active region of B δ-doping plane/2 nm i-Si0.5Ge0.5/1 nm i-Si/P δ-doping plane yielded a peak-to-valley current ratio (PVCR) of 1.14, resistive cutoff frequency (fr0) of 5.6 GHz, and a speed index of 23.3 mV/ps after rapid thermal annealing at 650°C for 1 min. To the authors' knowledge, these are the highest reported values for any epitaxially grown Si-based tunnel diode. Another RITD design with an active region of 1 nm p+ Si0.6Ge0.4/B δ-doping plane/4-nm iSi0.6Ge0.4/2 nm i-Si/P δ-doping plane and annealed at 825°C for 1 min had a PVCR of 2.9, an fr0 of 0.4 GHz, and a speed index of 0.2 mV/ps. A small signal model was established to fit the measured S11 data for both device designs. Approaches to increase fr0 are suggested based on the comparison between these two diodes. The two devices exhibit substantially different junction capacitance/bias relationships, which may suggest the confined states in the δ-doped quantum well are preserved after annealing at lower temperatures but are reduced at higher temperature annealing. A comprehensive dc/RF semi-physical model was developed and implemented in Agilent advanced design system (ADS) software. Instabilities in the negative differential resistance (NDR) region during dc measurements were then simulated. View full abstract»

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  • InP HEMT downscaling for power applications at W band

    Page(s): 2136 - 2143
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    We have developed new solutions for InP high-electron mobility transistor (HEMT) scaling for power applications at W band. We have shown that the use of a small barrier thickness in order to respect the aspect ratio for a 70-nm gate length results in a significant kink effect and high gate source capacitances. We have also shown through a theoretical study that a structure containing an InP layer between the cap layer and the barrier would support both the frequency performances and the breakdown voltage. Thus, we propose an HEMT structure containing a thick InP/AlInAs composite barrier and where the gate is buried into the barrier. This enables us to respect the aspect ratio and simultaneously to obtain an important drain current density without observing any kink effect. Moreover, we have applied this process to structures containing innovative large band-gap InP and InAsP channels. We have achieved the best frequency performances ever reached for an InP channel HEMT structure. Power measurements at 94 GHz were performed on these devices. The InAsP channel HEMT demonstrated a maximum output power of 260 mW/mm at 3 V of drain voltage with 5.9-dB power gain and a power-added efficiency of 11%. These results are favorably comparable to the state-of-the-art of InP-based HEMT at this frequency. View full abstract»

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  • Characterization and modeling of bias-stressed InGaP/GaAs collector-up tunneling-collector HBTs fabricated with boron-ion implantation

    Page(s): 2144 - 2149
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    To characterize and model the degradation of collector-up (C-up) heterojunction bipolar transistors (HBTs), we bias stress InGaP/GaAs C-up tunneling-collector HBTs (TC-HBTs) fabricated under various conditions for etching the collector mesas and of implanting boron ions into the extrinsic emitter. Contrary to the previous reports on reduction in collector current IC of bias-stressed emitter-up HBTs fabricated with ion implantation, no IC Gummel shift is observed in the case of C-up TC-HBTs, probably due to the lower damage resulting from the lower ion dosage. On the other hand, the base current of the bias-stressed C-up TC-HBTs increases with the decrease of the ion dose and with the increase of the collector mesa undercut under the collector electrode that is also used as an implant mask. We attribute the increased base current to the increased carrier recombination at the extrinsic base surface. Making the area of the emitter-base junction smaller than that of the base-collector junction-using electron-cyclotron resonance plasma etching together with lateral spreading of heavily implanted boron ions-results in a stable current gain even after a 1030-h testing at a junction temperature of 210°C and a collector current density of 402kA/cm. View full abstract»

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  • Characterization of MOS structures based on poly (3,3'''-dialkyl-quaterthiophene)

    Page(s): 2150 - 2156
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    Metal-polymer-oxide-silicon (MPOS) structures with poly(3,3'''-dialkyl-quaterthiophene) as an active semiconductor layer have been characterized by means of capacitance-voltage (C-V) methods at different ramping rates (dV/dt) for the voltage sweep in the quasi-static capacitance-voltage method (QCV), and at different frequencies (f) for the dynamic or high-frequency method (DCV or HCV). The observed dependency of the capacitance on ramping rate and frequency are explained with a frequency dependent carrier enhancement and a long relaxation time constant in the polymer. The surface modification of gate oxide is found to improve the carrier enhancement in the active polymer layer of MPOS. View full abstract»

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  • In-process functional testing of pixel circuit in AM-OLEDs

    Page(s): 2157 - 2162
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    This paper presents a functional testing scheme using a two-thin-film-transistor (TFT) pixel circuit of an active-matrix organic light-emitting display (AM-OLED). This pixel circuit and the co-operative electrical testing scheme can not only evaluate the characteristics of each TFT, but also determine the location of line and point defects in the TFT array. Information on defects can be used in a unique repair system that cutting and repairing these defects. Furthermore, the functional testing scheme can be applied as a part of yield management of the AM-OLED array process. View full abstract»

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  • Characterization of electrically active defects in photovoltaic detector arrays using laser beam-induced current

    Page(s): 2163 - 2174
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    One of the main limitations in the operability of modern infrared focal plane arrays of p-n junction diodes formed on molecular-beam epitaxy (MBE)-grown HgCdTe is the effect of localized defects. Such defects, including voids, triangles and microvoids, are a feature of the MBE growth regime and can compromise the performance of devices fabricated within the vicinity of electrically active defects. While such defects can often be identified visually, not all defects are electrically active such that they provide a current leakage path shunting the p-n junction of the individual photodiode. In this paper, the use of laser beam-induced current is proposed as a nondestructive characterization technique, and quantitative aspects of its use in the study of electrically active defects in photodiode arrays are examined. View full abstract»

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  • Self-consistent 2-D Monte Carlo Simulations of InSb APD

    Page(s): 2175 - 2181
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    Self-consistent Monte Carlo simulations are used to study the low noise and high gain potential of InSb avalanche photodiodes. It is found that for an electron-initiated avalanche, excess noise factors well below the minimum McIntyre value persist up to gain values of around 60 for a 3.2 μm avalanche region. For these very low noise values, it is found that multiplication has a very unusual voltage dependence which may be exploited for highly efficient novel low noise planar arrays operating at low voltage. View full abstract»

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  • An analytical hot-carrier induced degradation model in polysilicon TFTs

    Page(s): 2182 - 2187
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    Hot-carrier effects in n-channel polysilicon thin-film transistors (TFTs), with channel width W=10 μm and length L=10 μm, are investigated. An analytical model predicting the post-stress performance is presented, by treating the channel of the stressed device as a series combination of a damaged region extended over a length ΔL beside the drain and a region of length L-ΔL having the properties of the unstressed device. The apparent channel mobility is derived considering that the mobility of the damaged region is described with the mobility of amorphous Si TFTs, whereas the mobility of the undamaged region is described with the mobility of the virgin device. From the evolution of the static characteristics during stress, the properties of the damaged region with stress time are investigated. View full abstract»

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  • A ferroelectric associative memory technology employing heterogate FGMOS structure

    Page(s): 2188 - 2197
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    A ferroelectric associative memory technology has been developed using ferroelectric materials as a means of storing template vector information. In order to accommodate the ferroelectric memory cell to associative processing circuits, a heterogate floating-gate MOS structure has been developed. As a result, nondestructive reading of analog data written in the ferroelectric film has been made possible, allowing a wide voltage range of input signals to associative processing circuits. The concept has been experimentally verified using fabricated test devices and circuits. View full abstract»

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  • Physical insights regarding design and performance of independent-gate FinFETs

    Page(s): 2198 - 2206
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    Important physical insights regarding the design and performance of independent-gate FinFETs, e.g., the MIGFET , are gained from measured data and predictions from our process/physics-based double-gate (DG) MOSFET model (UFDG) in Spice3. Inversion charge-centroid shifting, modulated by gate biases as well as by quantum-confinement and short-channel effects, underlies the sensitivity of the MIGFET (front-gate) threshold voltage to the back-gate bias. MIGFET design and operation-mode options are examined for optimizing circuit applications. Further, novel design of a single-device RF mixer and a double-balanced counterpart using MIGFETs is studied with UFDG/Spice3. Reasonably good MIGFET mixers, with regard to conversion gain and linearity with small-size/low-voltage/low-power requirements, can be achieved with optimal biases on the two gates and good design of the MIGFET structure. View full abstract»

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  • Ultrathin strained-SOI by stress balance on compliant substrates and FET performance

    Page(s): 2207 - 2214
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    Ultrathin, strained-silicon-on-insulator (s-SOI) structures without a residual silicon-germanium (SiGe) underlayer have been fabricated using stress balance of bi-layer structures on compliant borophosphorosilicate glass (BPSG). The bi-layer structure consisted of SiGe and silicon films, which were initially pseudomorphically grown on a silicon substrate and then transferred onto BPSG by a wafer bonding and SmartCut process. The viscous flow of the BPSG during a high-temperature anneal then allowed the SiGe/Si bi-layer to laterally coherently expand to reach stress balance, creating tensile strain in the silicon film. No dislocations are required for the process, making it a promising approach for achieving high-quality strained-silicon for device applications. To prevent the diffusion of boron and phosphorus into the silicon from the BPSG, a thin nitride film was inserted between the bi-layer and BPSG to act as a diffusion barrier, so that a lightly doped, sub-10-nm s-SOI layer (0.73% strain) was demonstrated. N-channel MOSFETs fabricated in a 25-nm silicon layer with 0.6% strain showed a mobility enhancement of 50%. View full abstract»

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  • Highly reliable CVD-WSi metal gate electrode for nMOSFETs

    Page(s): 2215 - 2219
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    In this paper, we first propose an improved chemical vapor deposition (CVD) WSix metal gate suitable for use in nMOSFETs. We studied the relationship between the Si/W ratio of CVD-WSix film and electrical properties of MOSFETs. As a result, it was found that the Si/W ratio strongly affects carrier mobility and the reliability of gate oxide. In the case of higher Si/W ratio, both electron and hole mobility can be improved. For CVD-WSi3.9 electrode, electron mobility and hole mobility at 1.2 V of |Vg-Vth| are 331 and 78 cm2/V·s, respectively. These values are almost the same as those for n+-poly-Si electrode. The improvement of carrier mobility by controlling the Si/W ratio is due to suppression of fluorine contamination in gate oxide. F contamination at the Si/W ratio of 3.9 is found to be less than that at the Si/W ratio of 2.4 from XPS analysis. Workfunction of CVD-WSi3.9 gate estimated from C-V measurements is 4.3 eV. In CVD-WSi3.9 gate MOSFETs with gate length of 50 nm, a drive current of 636 μA/μm was achieved for off-state leakage current of 35 nA/μm at power supply voltage of 1.0 V. By using CVD-WSi3.9 gate electrode, highly reliable metal gate nMOSFETs can be realized. View full abstract»

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  • Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell

    Page(s): 2220 - 2226
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    A one-transistor memory cell on silicon-on-insulator, called floating-body cell (FBC), has been developed and demonstrated. Threshold voltage difference between the "0"-state and the "1"-state, which is a key parameter for realizing a large-scale memory by FBCs, is measured and analyzed using a 96 kb array diagnostic monitor (ADM). A function test of the ADM yielded a fail-bit probability of 0.002%. A new metric relating to the fail-bit probability, that is, the ratio of the threshold voltage difference over the total threshold voltage variation, is introduced and applied to the measurement results. Read current distributions are also evaluated for various operation voltages. This paper also investigates substrate bias dependence of the threshold voltage unique to fully-depleted devices. Channel impurity and substrate impurity concentration dependence of the threshold voltage are analyzed based on experimental data and device simulation. View full abstract»

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  • PZT MIM capacitor with oxygen-doped Ru-electrodes for embedded FeRAM devices

    Page(s): 2227 - 2235
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    An add-on-type, Pb(Zr,Ti)O3 (PZT) metal-insulator- (MIM) capacitor on Al multilevel interconnects is developed for embedded FeRAM devices, concluding that the oxygen-doping into the ruthenium (Ru) electrodes is crucial for obtaining large remnant polarization under a limited process temperature below 450°C. The oxygen-doped, Ru bottom-electrode with a granular structure reduces the PZT sputtering temperature below 450°C to obtain the ferroelectric perovskite-phase. On the other hand, oxygen doping into the Ru top-electrode suppresses the reductive damage at the interface between the top-electrode and the PZT, keeping the leakage current low. The PZT MIM capacitor with these oxygen-doped, Ru electrodes exhibits the remnant polarization of 21 μC/cm2 on the Al multilevel interconnects with no degradation of the interconnect reliability, thus applicable to the embedded FeRAM in 0.25 μm-CMOS logic LSIs. View full abstract»

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  • Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs

    Page(s): 2236 - 2242
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    This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed that the difference between the threshold voltage obtained with low and high drain bias, increases at lower temperatures for nMOSFETs, whereas it is weakly temperature-dependent for pMOSFETs. Experimental results and two-dimensional numerical simulations are used to support the analysis. The influence of applied back gate bias on threshold voltage variation is also studied. It is demonstrated that the higher doping level into the body region provided by the halo ion implantation associated to the floating-body increases both the multiplication factor and the parasitic bipolar gain as the temperature is lowered contributing to the threshold voltage degradation. The absence of halo implantation efficiently improves this degradation. The use of double gate structure, even with high body doping level, suppress the saturation threshold voltage degradation in cryogenic operation. View full abstract»

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  • Effect of material inhomogeneity on the open-circuit voltage of string ribbon Si solar cells

    Page(s): 2243 - 2249
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    The effect of material inhomogeneity on open-circuit voltage (VOC) of string ribbon Si solar cells is investigated by a combination of experimental results and a simple analytical model. Light beam-induced current (LBIC) measurements showed that a cell with no detectable defective region gave an efficiency of 15.9% with a VOC of 616 mV. However, a neighboring cell with highly defective regions covering 38% of its area, as determined by LBIC measurements, gave an efficiency of 14.1% with VOC of 578 mV. Another cell with 19% highly defective regions gave an efficiency of 15.0% with VOC of 592 mV. A simple and approximate analytical model was developed to quantify the loss in VOC on the basis of recombination intensity and the area fraction of defective regions. This model showed that the majority of the loss in VOC is associated with the most defective region, even if its area fraction is relatively small. View full abstract»

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  • A new scalable self-aligned dual-bit split-gate charge-trapping memory device

    Page(s): 2250 - 2257
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    Devices based on charge trapping are a promising solution for Flash memory scaling. The nonconductivity of their storage medium makes them more robust with respect to data loss by charge leakage through the bottom oxide, which, on the contrary sets a hard limit to floating-gate Flash scalability. Their simple processing, highly compatible with CMOS, makes them rapidly integrable into short-term solutions. The well-known SONOS concept however, still suffers from insufficient data throughput and retention. On the other hand, the recently proposed NROM concept, storing two bits in a cell, offers very interesting characteristics by using hot carrier based program/erase operations. However, important drawbacks remain, like insufficient isolation of the bits for scalability, high-power programming, and degradation of the retention after cycling. In this paper, we present a dual-bit trapping device which solves most of these problems by using a split-gate structure which was inspired by the HIMOS concept. The device has a fully self-aligned structure which allows for both bits to be physically isolated in the cell. Those features make it very scalable. Programming can be performed by the very efficient source-side injection mechanism, while erase is done by injection of band-to-band tunneling induced hot holes, which compensate for the trapped electrons. This leads to performances comparable to NROM but with lower power consumption, and lower operating voltages. View full abstract»

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  • Monte Carlo simulation of p- and n-channel GOI MOSFETs by solving the quantum Boltzmann equation

    Page(s): 2258 - 2264
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    The scaling characteristics of both n- and p-channel Ge-on-insulator (GOI) as well as silicon-on-insulator (SOI) MOSFETs with channel length ranging from 20-130 nm are studied by a two-dimensional self-consistent fullband Monte Carlo device simulator. The transistors' intrinsic performance and subthreshold characteristics are investigated for various channel lengths and Ge layer thicknesses. Our results indicate that both n- and p-channel GOI MOSFETs can be scaled down to the nanoregion, due to the nonstationary transport, especially for the p-channel device. More than 10% performance improvement for nMOS and about 20% for pMOS can be achieved in GOI even when channel length is scaled down to 20 nm, as compared to SOI devices. However, the GOI devices suffer from more severe short channel effect and have larger p-n junction leakage current as compared to SOI counterpart. For high-performance CMOS applications, GOI devices are feasible if the junction leakage can be reduced by optimizing the device structure. View full abstract»

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  • Depletion layer of gate poly-Si

    Page(s): 2265 - 2271
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    The depletion effects of gate poly-Si are investigated in detail taking into consideration the fact that many-body effects due to carrier-carrier and carrier-ion interactions are different at the surface than in a bulk of the gate poly-Si. All calculations are self-consistently performed including an incomplete ionization of activated impurities in an iterative manner. As a result, it is found that the surface part of these interactions affects the equivalent oxide thickness determined by the capacitance-voltage fitting, and that the bulk part affects the determination of flat band potential. It is also found that the surface of the gate poly-Si is incompletely depleted, and the depletion layer is then wider than calculated when assuming the complete depletion (NS/ND). The width of the incomplete depletion layer is studied in detail for the first time. View full abstract»

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  • Global interconnect width and spacing optimization for latency, bandwidth and power dissipation

    Page(s): 2272 - 2279
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    This paper addresses a novel methodology optimizing global interconnect width and spacing for International Technology Roadmap for Semiconductors technology nodes. Global interconnects with and without buffer insertion are considered. The effects of the width and spacing of global interconnects on performance, such as delay, bandwidth, total repeater area and energy dissipation, are analyzed. The product of delay and bandwidth is used as the figure of merit for simultaneous short latency and large bandwidth and the proposed methodology can optimize global interconnects for the maximal figure of merit. It is demonstrated that buffers should not be inserted in global interconnects if interconnect length is shorter than a critical length, which is a constant for a given technology. For global interconnects with buffer insertion, the optimal width and spacing have analytical expressions and are constants for a given technology. For global interconnects without buffer insertion, the optimal width and spacing are dependent on both the technology parameters and interconnect length and can be computed numerically. View full abstract»

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  • A new backscattering model giving a description of the quasi-ballistic transport in nano-MOSFET

    Page(s): 2280 - 2289
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    A backscattering model suitable for compact modeling of nanoscale MOSFET is developed within the Landauer flux-scattering theory. To describe the quasi-ballistic transport, a new backscattering model based on the accurate determination of ballistic and backscattering probabilities along the channel is developed. This model is based on a careful analysis of transport in device using Monte Carlo simulation. This model allows us to display the main physical quantities along the channel and to accurately describe the quasi-ballistic transport and its effects on current-voltage characteristics. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology