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Circuits, Devices and Systems, IEE Proceedings G

Issue 6 • Date Dec 1991

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Displaying Results 1 - 19 of 19
  • Semisystolic architecture for fast Hartley transform: decimation in frequency and radix 2

    Page(s): 651 - 660
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    A parallel architecture is presented for the calculation of the fast Hartley transform (FHT) radix 2 which is adequate for its implementation in VLSI technology. As a first step, a constant geometry (decimation in frequency) algorithm for computing the FHT has been developed. The circuit proposed is characterised by its modular design and its interconnection regularity. It can be considered as semi-systolic. It is highly efficient and flexible. It permits the computation of arbitrarily sized FHTs as a consequence of data recirculation over the processing units in all the stages of the transform. The number of communications is the least possible due to the use of a constant geometry algorithm. Each calculation stage requires N/4Q cycles where N and Q are the length of the input real sequence and the number of processors (N =22, Q=2q), respectively. The system proposed calculates the FHT in n stages, therefore, the total calculation time is (N log2 N)/4Q cycles View full abstract»

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  • Bound on inputs to neurons of Hopfield continuous-variable neural network

    Page(s): 671 - 672
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (60 KB)  

    It is demonstrated that the inputs to the neurons of Hopfield continuous-variable neural network are bounded, which is useful for designing the realisable analogue electrical circuits of this kind of neural system View full abstract»

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  • Characteristics of δ-doped FETs in GaAs

    Page(s): 633 - 636
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    Experimental data is presented on several batches of δ-doped field effect transistors grown by molecular beam epitaxy in GaAs. The expected linear transfer characteristics were observed and values of extrinsic transconductance comparable with the best values reported elsewhere were obtained. Excellent consistency was obtained between devices fabricated on the same layer, and between batches grown on different layers. Depletion and enhancement characteristics are shown. Reasonable agreement was obtained between the measured characteristics and a simple theory based on a piecewise linear approximation to the velocity-field curve View full abstract»

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  • Small signal nonquasistatic models for GaAs field effect transistors for implementation in SPICE. I. Modulation-doped field effect transistors (MODFETs)

    Page(s): 735 - 748
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    A general small signal nonquasistatic model for modulation doped field effect transistors (MODFETs) is presented. The model is valid for devices operating in both linear and saturation regions. The two dimensional electron gas (2DEG) current is modelled. The current flowing in the parasitic doped AlGaAs layer is considered elsewhere. In both cases, admittance parameters (Y-parameters) are derived and used to build SPICE-like equivalent circuits. The proposed model can, therefore, be easily implemented in SPICE for microwave and high-frequency analogue circuit analysis. The results show that, for a 1 μm gate length MODFET, the error is less than 5% at 86 GHz View full abstract»

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  • Improved minimax optimisation algorithms and their application in the design of recursive digital filters

    Page(s): 724 - 730
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    A technique that can improve the performance of available optimisation algorithms, in applications where the objective function involves the sampling of a function with respect to an independent variable, is proposed. The technique is then applied in conjunction with two well known minimax algorithms for the design of recursive digital filters. Extensive experimental results show that the new technique reduces the approximation errors significantly and eliminates the problem of spikes in the error function. Although the amount of computation needed to carry out a design for a fixed density of grid points is increased somewhat, improved robustness is achieved, which allows a reduced density of grid points and eliminates waste of computational effort in unsuccessful designs View full abstract»

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  • Novel modification on SPICE BJT model to obtain extended accuracy

    Page(s): 673 - 678
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    A modification on the SPICE BJT model with the purpose of extending the accuracy range is proposed. The proposed model improves the representation of the Early effect for forward and inverse operating regions. Another main improvement is on the βF-IC and βR-I E dependences at high-injection levels achieved by introducing one extra model parameter and by modifying the normalised total base-charge expression. The model provides new possibilities in analogue IC design such as accurate simulation of low-distortion building blocks View full abstract»

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  • Analogue adaptive neural network circuit

    Page(s): 717 - 723
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    Current integrated circuits realising neural networks take up too much area for implementing synapses. The authors present a one-transistor (1T) synapse circuit that uses a single MOS transistor, which is more efficient for VLSI implementation of adaptive neural networks, compared to other synapse circuits. This 1T synapse circuit can be used to implement multiply/divide/sum circuits to realise an adaptive neural network. The feasibility of using this circuit in adaptive neural networks is demonstrated by a 4-bit analogue-to-digital converter circuit, based on the Hopfield modified neural network model, with an analogue LMS adaptive feedback. DC and transient studies show that 1T synapse circuits with an analogue adaptive feedback circuit can be used more efficiently for VLSI implementation of adaptive neural networks View full abstract»

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  • Characteristics of GaAs graded-period delta-doped superlattice

    Page(s): 629 - 632
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    In the paper, the characteristics of a GaAs graded-period delta-doped superlattice grown by molecular beam epitaxy are studied. It is shown that a novel S-shaped negative differential conductivity (NDC) occurs both at 300 K and 77 K. An N-shaped NDC due to the temperature-induced tunnelling effect is observed at 300 K. In addition, a two-state avalanche multiplication process, i.e. a middle quasistable region, is seen at 77 K. Finally, there is an interesting hysteresis phenomenon due to the trapped holes created by the avalanche multiplications View full abstract»

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  • Comments on `Algorithm for reducing circuit equations in computer applications' [and reply]

    Page(s): 733 - 734
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    For the original article see ibid., vol.137, no.1, p.16-20 (1990). The commenters point out that the above paper by S. Natarajan contains statements concerning the use of computers for circuit analysis that differ with their experience. In particular, the author's claim that sparse matrix solvers are not suitable for PC computers, because of their memory requirements, cannot be justified according to the commenters. In reply the author accepts that the initial comment is justified because of a mistake in one of the sentences in the paper where `infinite gain' should read `finite gain'. However, the rest of the comments concerning the use of PC computers are considered unjustified and the author goes on to explain why this is the case View full abstract»

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  • General approach for development of CAD-oriented analytical device models

    Page(s): 637 - 650
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    Accuracy and simplicity of analytical device models are fundamental requisites in circuit simulation and particularly crucial for current VLSI technologies. A model to be used in a circuit simulator is usually developed starting from a zero-order physically based model and adding several empirical parameters derived from a fitting procedure. In this semi-empirical scheme, however, no criteria are posed to satisfy the previously mentioned requisites. The authors provide a general approach for developing efficient device models in terms of accuracy and simplicity. For this purpose a fundamental definition of good approximation based on a given condition on the error between model and measured data is proposed and a measure for complexity of the model is defined. On the basis of these general concepts it is shown that under general conditions it is possible to derive a piecewise continuous function (PCF) from a zero-order model as a good approximation of measured data. Conditions to obtain a representation with minimum complexity are also provided View full abstract»

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  • Space and time continuous lumped transmission line model

    Page(s): 661 - 670
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    A lumped transmission line model, based on polynomial approximation and the least squares method, is deduced and investigated. The model enables the line voltage and current to be determined approximately for arbitrary points along the line and at arbitrary times. The model is not restricted to lossless lines, nor to the sinusoidal steady state. Further, some examples are given showing how the transmission line model can be extended to include arbitrary linear terminal dynamics. The model is in the time domain as well as in the frequency domain, and is compared to analytically obtained responses View full abstract»

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  • Systematic realisation of binary and multivalued logic functions using charge coupled building blocks

    Page(s): 694 - 702
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    The suitability of basic CCD gates for the synthesis and realisation of binary and multi-valued logic (MVL) functions is investigated. Systematic design methods for these functions are presented using the proposed building blocks. Characterisation of functions in terms of the type of CCD gate required for their implementation is introduced and used to introduce two functionally complete sets of operations in the charge domain. Use of these operations in the realisation of binary functions is explained and illustrative examples are given. Realisation of some important binary and MVL circuits is also presented. A high-level (macro-cell-like) synthesis approach is proposed for the realisation of functions using CCD building blocks. It does not address circuit-level problems such as charge level degradation, delay synchronisation, layout constraints, etc. Remedies for these problems, using, for example, charge regeneration, charge-to-voltage conversion, etc., may change the cost set up for individual blocks. However, they do not influence the synthesis approaches presented View full abstract»

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  • Comparison of four CMOS transconductors for fully integrated analogue filter applications

    Page(s): 683 - 688
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    An analysis of four transconductors based on CMOS transistors operating in saturation is presented and computer simulated performances are compared. It is shown that an antiphase source-coupled pair offers superior tuning characteristics and exhibits low distortion at large input drives View full abstract»

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  • Switched-capacitor pipelined logarithmic A/D and D/A convertors

    Page(s): 714 - 716
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    The authors present two switched-capacitor circuits with modest complexity to implement a pipelined logarithmic digital-analogue convertor (LDAC) and logarithmic analogue-digital convertor (LADC), respectively, which spend only one clock time per conversion. In addition, the effect of the capacitor-ratio mismatch on the conversion errors of the convertor circuits is discussed. Hence, from the available maximum capacitor-ratio value and mismatch of the present integrated circuit (IC) technology, the feasible bit length of the pipelined LDAC and LADC can be computed View full abstract»

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  • Small signal nonquasistatic models for GaAs field effect transistors for implementation in SPICE. II. Metal semiconductor field effect transistors (MESFETs)

    Page(s): 749 - 755
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    For pt.I see ibid., vol.138, no.6, p.735-48 (1991). A nonquasistatic model for GaAs metal semiconductor field effect transistors (MESFETs) is developed. The active distributed transmission line analogy is used to obtain frequency dependent Y-parameter relationships. Implementing the Y-parameters using R, L and C elements, a SPICE-like small signal equivalent circuit is built. This model can be used for the parasitic MESFETs of modulation doped field effect transistors (MODFETs) as well as regular MESFET structures View full abstract»

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  • Simple sufficient test for stability of two-dimensional recursive digital filters

    Page(s): 731 - 732
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (84 KB)  

    The design of recursive digital filters is relatively simple, but such filters introduce a major problem of stability. This problem has been the subject of intensive research during recent decades and the trend is towards finding sufficient conditions, because necessary and sufficient conditions are difficult to find or to test. In this correspondence, a different proof of the sufficient stability condition, recently established by A.J. Kanellakis and N.J. Theodorou (see ibid., vol.134, no.5, p.246-7, 1987) for the two-dimensional case is proposed View full abstract»

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  • Switched capacitor circuit synthesis using voltage inversion principles

    Page(s): 703 - 713
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    The synthesis of switched capacitor circuits of a wide variety of types is presented. First and second order sections for cascade and multifeedback filter realisations, integrators for functional simulation of classical LCR filters and simulated impedances for topological element simulation of LCR filters are considered. A principle of voltage inversion is shown to be a common aspect for all these types of circuit realisation. After considering techniques for the realisation of such voltage inversion, the principle is applied to a number of required subcircuits and hence to a number of diverse filter examples. In general, the circuits developed, which have a generic similarity, have a number of attractive features including the possibility of realising bilinear transformed transfer functions, minimisation of the number of amplifiers required and ability to apply scaling for optimum dynamic range and capacitor area minimisation. One of the results of this approach based on voltage inversion is a single amplifier, bilinear bandpass biquad View full abstract»

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  • Current flow between neighbouring trench cells triggered by alpha particle strikes

    Page(s): 689 - 693
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    The track of an alpha particle that traverses two adjacent trench-type memory cells acts as a conductive channel because of the high concentration of generated carriers so that, where the hit cells have different potential levels, a current flow is triggered which leads to an additional charge collection. The process of charge transfer between the cells owing to alpha particle striking is described by an equivalent circuit, which allows rapid calculation of the current through the parasitic channel, taking into account the total angle and energy spectrum of alpha particle radiation. It is found that the collected charge is appreciably increased only when the trench distance is comparable to the width of the p-n spacecharge region of the cell at high-level potential and when the alpha particle tracks run approximately parallel to the semiconductor surface View full abstract»

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  • Algebra system for ECL circuits

    Page(s): 679 - 682
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    Based on the distinction of two kinds of algebra, the action principle of ECL circuits is analysed. Threshold comparison operations and current switching operation connecting two kinds of algebra systems, in accordance with the interaction between the switching elements and signals, is proposed. According to the discussion of the properties of operations, an algebra system for ECL circuits is established. The design example realising exclusive-OR operation shows that the theory can not only explain the traditional design of ECL circuits in essence, but also develops a simpler design methodology for ECL circuits View full abstract»

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