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Selected Areas in Communications, IEEE Journal on

Issue 8 • Date Oct 1991

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Displaying Results 1 - 17 of 17
  • A 1.5 Gb/s 8×8 cross-connect switch using a time reservation algorithm

    Publication Year: 1991 , Page(s): 1308 - 1317
    Cited by:  Papers (18)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB)  

    An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s View full abstract»

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  • Practical implementation and packaging technologies for a large-scale ATM switching system

    Publication Year: 1991 , Page(s): 1280 - 1288
    Cited by:  Papers (36)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (960 KB)  

    The practical implementation of a trial large-scale asynchronous transfer mode (ATM) switching system and its packaging technologies are described. The architecture of the ATM switching system is discussed with an emphasis on system scalability. A building block architecture in which switching capacity can be expanded in a modular fashion is introduced. The design of the ATM switching system, including the ATM switch element, is described. The implementation of the VLSIs for the ATM switch which realize a highly modular system is explained. Bit-slice techniques are effectively used to realize a high-speed switch element as a CMOS VLSI chipset. An edge-to-edge orthogonal packaging technique is also presented View full abstract»

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  • A recursive modular terabit/second ATM switch

    Publication Year: 1991 , Page(s): 1161 - 1172
    Cited by:  Papers (38)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (980 KB)  

    The author proposes a recursive modular architecture for a very large scale asynchronous transfer mode (ATM) switch. By extending the concept of the original knockout switch, the cell filtering and contention resolution functions are distributed over many small switch elements, which are arranged in a crossbar structure. The output ports of a switch fabric are partitioned into a number of groups by a novel grouping network to permit sharing of the routing paths in the same group. This partitioning and sharing concept is applied recursively to construct the entire switch elements. The technique of channel grouping for trunk circuits can be incorporated in the proposed ATM switch to improve the cell loss/delay performance while the cells' sequences are retained. A prototype circuit for the key switch element has been designed, and it has been shown that more than 4000 of the switch elements can be integrated into a VLSI chip with existing CMOS 1-μm technology View full abstract»

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  • Autonet: a high-speed, self-configuring local area network using point-to-point links

    Publication Year: 1991 , Page(s): 1318 - 1335
    Cited by:  Papers (149)  |  Patents (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1732 KB)  

    Autonet is a self-configuring local area network composed of switches interconnected by 100 Mb/s, full-duplex, point-to-point links. The switches contain 12 ports that are internally connected by a full crossbar. Switches use cut-through to achieve a packet forwarding latency as low as 2 ms/switch. Any switch port can be cabled to any other switch port or to a host network controller. A processor in each switch monitors the network's physical configuration. A distributed algorithm running on the switch processor computes the routes packets are to follow and fills in the packet forwarding table in each switch. With Autonet, distinct paths through the set of network links can carry packets in parallel, allowing many pairs of hosts to communicate simultaneously at full link bandwidth. A 30-switch network with more than 100 hosts has been the service network for Digital's Systems Research Center since February 1990 View full abstract»

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  • Sunshine: a high performance self-routing broadband packet switch architecture

    Publication Year: 1991 , Page(s): 1289 - 1298
    Cited by:  Papers (116)  |  Patents (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB)  

    The authors present a high-performance self-routing packet switch architecture, called Sunshine, that can support a wide range of services having diverse performance objectives and traffic characteristics. Sunshine is based on Batcher-banyan networks and achieves high performance by utilizing both internal and output queuing techniques within a single architecture. This queuing strategy results in an extremely robust and efficient architecture suitable for a wide range of services. An enhanced architecture allowing the bandwidth from an arbitrary set of transmission links to be aggregated into trunk groups to create high bandwidth pipes is also presented. Trunk groups appear as a single logical port on the switch and can be used to increase the efficiency of the switch in an extremely bursty environment or to increase the access bandwidth for selected high-bandwidth terminations. Simulation results are presented View full abstract»

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  • 32×32 shared buffer type ATM switch VLSIs for B-ISDNs

    Publication Year: 1991 , Page(s): 1239 - 1247
    Cited by:  Papers (69)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (940 KB)  

    A set of 0.8 μm CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32×32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32×32 switching board to achieve large-scale switching systems such as 256×256 or 1024×1024 switches are discussed View full abstract»

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  • A large ATM switch based on memory switches and optical star couplers

    Publication Year: 1991 , Page(s): 1348 - 1360
    Cited by:  Papers (15)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1180 KB)  

    The authors propose a large asynchronous transfer mode (ATM) switch architecture based on memory switches of the type being developed by several research groups and on optical star couplers. Fast contention resolution makes it possible to combine a number of these modules, memory switches, and optical stars in order to attain a capacity of 2.5 Tb/s. This switch architecture has a relatively small failure group size of 128 STS-3 lines out of a total of 16384. The scaling of the switch to smaller capacities is discussed, showing how tradeoffs in the various parameters can be used to overcome particular technological limitations. Fault tolerance and recovery schemes are presented, showing that with minimal increase to the switch complexity and cost, a very reasonable fault recovery scheme is available for almost every sort of failure View full abstract»

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  • A fault-tolerant switching network for B-ISDN

    Publication Year: 1991 , Page(s): 1218 - 1226
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (772 KB)  

    The author proposes a self-routing fault-tolerant switching network for asynchronous transfer mode (ATM) switching systems. The network has many subswitches to enhance the fault tolerance of the conventional multistage interconnection network which only has a unique path. The subswitches provide large numbers of alternative paths between switching stages and allow the network to tolerate multiple paths. The routing algorithm is quite simple. The paths can also be used to route cells under the condition that internal cell contentions occur in switching elements. A reliability analysis shows a quantitative measurement of the improvement in fault tolerance as compared with previously presented fault-tolerant networks. A performance analysis and simulation results show that the proposed network has a high level of maximum throughput. In addition, that level of throughput is maintained with reasonable cell delay even though the number of faulty components increases in the network View full abstract»

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  • Physical design issues for very large ATM switching systems

    Publication Year: 1991 , Page(s): 1227 - 1238
    Cited by:  Papers (20)  |  Patents (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1172 KB)  

    The authors examine the physical design issues associated with terabit/second switching systems, particularly with regard to the customer access portion of the switch. They determine the physical design requirements in the areas of backplane interconnections, integrated circuit packaging, and circuit board technology and identify areas where existing- or near-future physical design technologies are inadequate to meet the requirements of this application. A new 3D interconnection architecture that solves some of the problems encountered at the backplane level is suggested. It is also suggested that multichip module technology will help meet some of the speed and density requirements at the chip packaging level. Some of the system-level consequences of the proposed model are discussed View full abstract»

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  • Weighted round-robin cell multiplexing in a general-purpose ATM switch chip

    Publication Year: 1991 , Page(s): 1265 - 1279
    Cited by:  Papers (151)  |  Patents (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1448 KB)  

    The authors present the architecture of a general-purpose broadband-ISDN (B-ISDN) switch chip and, in particular, its novel feature: the weighted round-robin cell (packet) multiplexing algorithm and its implementation in hardware. The flow control and buffer management strategies that allow the chip to operate at top performance under congestion are given, and the reason why this multiplexing scheme should be used under those circumstances is explained. The chip architecture and how the key choices were made are discussed. The statistical performance of the switch is analyzed. The critical parts of the chip have been laid out and simulated, thus proving the feasibility of the architecture. Chip sizes of four to ten links with link throughput of 0.5 to 1 Gb/s and with about 1000 virtual circuits per switch have been realized. The results of simulations of the chip are presented View full abstract»

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  • Efficient modeling of merging and splitting processes in large networking structures

    Publication Year: 1991 , Page(s): 1336 - 1347
    Cited by:  Papers (11)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1088 KB)  

    Simple models are developed for the description of a first-order Markovian (bursty) process modulated by merging and/or (independent or correlated) splitting operations. The models can be adopted for the packet traffic description in large networking structures, supporting multimedia packet traffic. This is due to the fact that the complexity of these models does not change as the number of points of transformation increases. The bursty traffic model is capable of describing a variety of packet sources. The induced packet delay at the merging points is evaluated. A queuing system is studied for this purpose under a general class of arrival processes, which include the adopted packet traffic models. Numerical results are obtained and are compared with simulations whenever approximations are involved View full abstract»

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  • A reconfigurable ATM switch fabric for fault tolerance and traffic balancing

    Publication Year: 1991 , Page(s): 1205 - 1217
    Cited by:  Papers (4)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1132 KB)  

    A large-scale asynchronous transfer mode (ATM) switch fabric that can be constructed with currently feasible technology is proposed. Based on analysis of the technology, it is found that module interconnection becomes the bottleneck for a large fast packet switch. Fault tolerance for the switch is achieved by dynamic reconfiguration of the module interconnection network. The design improves system reliability with relatively low hardware overhead. An abstract model of the replacement problem for the design is presented, and the problem is transformed into a well-known assignment problem. The maximum fault tolerance is found, and a fast replacement algorithm is given. The reconfiguration capability can also be used to ameliorate imbalanced traffic flows. The authors formulate this traffic flow assignment problem for the switch fabric and show that the problem is NP-hard. A simple heuristic algorithm is proposed, and an example is given View full abstract»

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  • A scalable ATM switching system architecture

    Publication Year: 1991 , Page(s): 1299 - 1307
    Cited by:  Papers (21)  |  Patents (34)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB)  

    The architecture of an asynchronous transfer mode (ATM) switching system for prototype applications is presented. The general concept to upgrade the existing ISDN switch with an ATM module is introduced, and the building blocks of this ATM module are described in detail. Switching of ATM cells is performed in a single application-specific integrated circuit (ASIC). ASICs can be cascaded to form large switching modules. Peripheral modules interface the ATM switch to external transmission systems and perform all ATM-related functions, including means for redundancy of the switching network. The redundancy scheme tolerates single failures without affecting the user information. A switching network architecture is shown to be capable of fulfilling varying demands in terms of the number of ports for ATM switches and cross connects, concentrators, and multiplexers View full abstract»

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  • A one-chip scalable 8*8 ATM switch LSI employing shared buffer architecture

    Publication Year: 1991 , Page(s): 1248 - 1254
    Cited by:  Papers (39)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (660 KB)  

    The authors present a one-chip scalable 8×8 shared buffer switch LSI which includes a 256-cell buffer. Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8 μm BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated View full abstract»

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  • Rerouting network: a high-performance self-routing switch for B-ISDN

    Publication Year: 1991 , Page(s): 1194 - 1204
    Cited by:  Papers (43)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB)  

    A high-performance self-routing switch is proposed for ATM (asynchronous transfer mode) switch systems. Switching performance is enhanced by a rerouting algorithm applied to a particular multistage interconnection algorithm. The interconnection algorithm offers many access points to the output and resolves output contention by layering buffers at each switching stage. The author analyzes switching performance and shows that this switch can be easily engineered to have high throughput and low cell loss probability by increasing the number of switching stages. The author also illustrates that the number of switching stages required for a given cell loss probability shows gradual growth with increasing switch size. Analysis shows that the proposed switch is robust even with respect to nonuniform traffic View full abstract»

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  • Architecture, performance, and implementation of the tandem banyan fast packet switch

    Publication Year: 1991 , Page(s): 1173 - 1193
    Cited by:  Papers (66)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1932 KB)  

    The authors propose a new space-division fast packet switch architecture based on banyan interconnection networks, called the tandem banyan switching fabric (TBSF). It consists of placing banyan networks in tandem, offering multiple paths from each input to each output, thus overcoming in a very simple way the effect of conflicts among packets (to which banyan networks are prone) and achieving output buffering. From a hardware implementation perspective, this architecture is simple in that it consists of several instances of only two VLSI chips, one implementing the banyan network and the other implementing the output buffer function. The basic structure and operation of the tandem banyan switching fabric are described, and its performance is discussed. The authors propose a modification to the basic structure which decreases the hardware complexity of the switch while maintaining its performance. An implementation of the banyan network using a high-performance BiCMOS sea-of-gates on 0.8-μm technology is reported View full abstract»

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  • Design and technology aspects of VLSIs for ATM switches

    Publication Year: 1991 , Page(s): 1255 - 1264
    Cited by:  Papers (21)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (920 KB)  

    A system concept based on a multipath self-routing switching principle and on an internal transfer mode using multislot cells is introduced. With the utilization of a shared buffer memory structure, this concept allows for a single-chip realization of the switching elements and fulfils important system requirements like fault tolerance, independence of the switch core from external data formats and traffic characteristics, and modular extendibility from small to very large systems. An example implementation of the concept with the resulting functional partitioning in boards and chips is given. Performance study results, as a basis for dimensioning, are also presented. The most important design aspects and a possible tool chain exploiting a hardware description language, logic simulator, and logic compiler are highlighted View full abstract»

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Aims & Scope

IEEE Journal on Selected Areas in Communications focuses on all telecommunications, including telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation.

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Editor-in-Chief
Muriel Médard
MIT